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Intel(R) 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)
Datasheet
July 2001
Order Number: 298338-001
Intel 830MP Chipset
(R)
R
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 830MP Graphics-Memory Controller Hub- Mobile (GMCH-M) product may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel(R) is a registered trademark of Intel Corporation and its subsidiaries in the United States and other countries. *Other brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copyright (c) Intel Corporation 2001
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Contents
1 2 Introduction .................................................................................................................................13 1.1 Document References ...................................................................................................13 Overview.....................................................................................................................................14 2.1 Terminology ...................................................................................................................15 2.2 System Architecture.......................................................................................................16 2.3 Host Interface.................................................................................................................16 2.4 System Memory Interface ..............................................................................................16 2.5 AGP Interface ................................................................................................................17 Signal Description.......................................................................................................................18 3.1 Host Interface Signals....................................................................................................20 3.2 System Memory Interface ..............................................................................................22 3.3 AGP Interface Signals....................................................................................................23 3.3.1 AGP Addressing Signals .............................................................................23 3.3.2 AGP Flow Control Signals ...........................................................................24 3.3.3 AGP Status Signals .....................................................................................24 3.3.4 AGP Clocking Signals - Strobes .................................................................25 3.3.5 PCI Signals - AGP Semantics ....................................................................26 3.3.6 PCI Pins During PCI Transactions on AGP Interface..................................27 3.4 Hub Interface Signals.....................................................................................................28 3.5 Clocking and Reset........................................................................................................29 3.6 Intel 830MP Reserve Signals ........................................................................................30 3.6.1 Graphics Memory Interface .........................................................................30 3.6.2 Dedicated Digital Video Port (DVOA) ..........................................................31 3.7 Analog Display ...............................................................................................................32 3.7.1 Display Control Signals................................................................................33 3.8 Voltage References, PLL Power....................................................................................34 3.9 Strap Signals..................................................................................................................35 Register Description ...................................................................................................................36 4.1 Conceptual Overview of the Platform Configuration Structure ......................................36 4.2 Routing Configuration Accesses to PCI0 or AGP/PCI...................................................37 4.2.1 Intel 82830MP GMCH-M Configuration Cycle Flow Charts ........................38 4.2.2 PCI Bus Configuration Mechanism..............................................................38 4.2.3 PCI Bus #0 Configuration Mechanism.........................................................39 4.2.4 Primary PCI and Downstream Configuration Mechanism ...........................39 4.2.5 AGP/PCI1 Bus Configuration Mechanism ...................................................40 4.2.6 Internal GMCH-M Configuration Register Access Mechanism ...................42 4.3 GMCH-M Register Introduction .....................................................................................42 4.4 I/O Mapped Registers ....................................................................................................43 4.4.1 CONFIG_ADDRESS - Configuration Address Register ..............................43 4.4.2 CONFIG_DATA - Configuration Data Register ...........................................45 4.5 GMCH-M Internal Device Registers ..............................................................................45 4.5.1 SDRAM Controller/Host-hub Interface Device Registers - Device #0.........46 4.5.1.1 VID - Vendor Identification Register - Device #0 ............................48 4.5.1.2 DID - Device Identification Register - Device #0.............................48 4.5.1.3 PCICMD - PCI Command Register - Device #0 .............................49 4.5.1.4 PCISTS - PCI Status Register - Device #0 .....................................50
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4.5.1.5 4.5.1.6 4.5.1.7 4.5.1.8 4.5.1.9 4.5.1.10 4.5.1.11 4.5.1.12 4.5.1.13 4.5.1.14 4.5.1.15 4.5.1.16 4.5.1.17 4.5.1.18 4.5.1.19 4.5.1.20 4.5.1.21 4.5.1.22 4.5.1.23 4.5.1.24 4.5.1.25
4.5.2
RID - Revision Identification Register - Device #0 ......................... 51 SUBC - Sub-Class Code Register - Device #0 .............................. 51 BCC - Base Class Code Register - Device #0 ............................... 51 MLT - Master Latency Timer Register - Device #0......................... 52 HDR - Header Type Register - Device #0 ...................................... 52 APBASE - Aperture Base Configuration Register - Device #0...... 53 SVID - Subsystem Vendor ID - Device #0..................................... 54 SID - Subsystem ID - Device #0.................................................... 54 CAPPTR - Capabilities Pointer - Device #0 .................................. 54 RRBAR - Register Range Base Address Register - Device #0 ..... 55 GCC0 - GMCH Control Register #0 - Device #0 ............................ 56 GCC1--GMCH Control Register #1 - Device #0 ............................ 58 FDHC - Fixed DRAM Hole Control Register - Device #0 ............... 58 PAM(6:0) - Programmable Attribute Map Registers - Device #0 ... 59 DRB -- DRAM Row Boundary Register - Device #0 ..................... 62 DRA -- DRAM Row Attribute Register - Device #0 ....................... 63 DRT--DRAM Timing Register - Device #0 .................................... 64 DRC - DRAM Controller Mode Register - Device #0...................... 66 DTC - DRAM Throttling Control Register - Device #0. ................... 68 SMRAM - System Management RAM Control Register - Device #070 ESMRAMC - Extended System Management RAM Control Register - Device #0 ....................................................................... 71 4.5.1.26 ERRSTS - Error Status Register - Device #0 ............................... 72 4.5.1.27 ERRCMD - Error Command Register - Device #0 ......................... 73 4.5.1.28 ACAPID - AGP Capability Identifier Register - Device #0 .............. 75 4.5.1.29 AGPSTAT - AGP Status Register - Device #0 ............................... 76 4.5.1.30 AGPCMD - AGP Command Register - Device #0.......................... 77 4.5.1.31 AGPCTRL - AGP Control Register - Device #0 ............................. 78 4.5.1.32 AFT - AGP Functional Test Register - Device #0 ......................... 78 4.5.1.33 APSIZE Aperture Size - Device #0 ............................................. 78 4.5.1.34 ATTBASE Aperture Translation Table Base Register - Device #079 4.5.1.35 AMTTAGP Interface Multi-Transaction Timer Register - Device #0 .................................................................................................. 79 4.5.1.36 LPTTLow Priority Transaction Timer Register - Device #0 ........ 80 4.5.1.37 BUFF_SC - System Memory Buffer Strength Control Register Device #0........................................................................................ 81 4.5.1.37.1 SDR Drive Strength Register Description .................... 81 HOST-AGP Bridge Registers - Device #1................................................... 84 4.5.2.1 VID1 - Vendor Identification Register - Device #1.......................... 85 4.5.2.2 DID1 - Device Identification Register - Device #1 .......................... 85 4.5.2.3 PCICMD1 - PCI-PCI Command Register - Device #1.................... 86 4.5.2.4 PCISTS1 - PCI-PCI Status Register - Device #1 ........................... 87 4.5.2.5 RID1 - Revision Identification Register - Device #1 ....................... 87 4.5.2.6 SUBC1 - Sub-Class Code Register - Device #1 ............................ 88 4.5.2.7 BCC1 - Base Class Code Register - Device #1 ............................. 88 4.5.2.8 MLT1 - Master Latency Timer Register - Device #1....................... 88 4.5.2.9 HDR1 - Header Type Register - Device #1 .................................... 89 4.5.2.10 PBUSN - Primary Bus Number Register - Device #1..................... 89 4.5.2.11 SBUSN - Secondary Bus Number Register - Device #1 ............... 89 4.5.2.12 SUBUSN - Subordinate Bus Number Register - Device #1 ........... 90 4.5.2.13 SMLT - Secondary Master Latency Timer Register - Device #1.... 90 4.5.2.14 IOBASE - I/O Base Address Register - Device #1 ......................... 91 4.5.2.15 IOLIMIT - I/O Limit Address Register - Device #1 .......................... 91 4.5.2.16 SSTS - Secondary PCI-PCI Status Register - Device #1.............. 92
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MBASE - Memory Base Address Register - Device #1 ..................93 MLIMIT - Memory Limit Address Register - Device #1 ...................93 PMBASE - Prefetchable Memory Base Address Register - Device #1 ...................................................................................................95 PMLIMIT - Prefetchable Memory Limit Address Register - Device #1 ...................................................................................................95 BCTRL - PCI-PCI Bridge Control Register - Device #1 ..................96 ERRCMD1 - Error Command Register - Device #1.......................98
Functional Description ................................................................................................................99 5.1 System Address Map.....................................................................................................99 5.1.1 System Memory Address Ranges ...............................................................99 5.1.2 Compatibility Area......................................................................................101 5.1.2.1 DOS Area (00000h-9FFFFh) ........................................................102 5.1.2.2 Legacy VGA Ranges (A0000h-BFFFFh) ......................................102 5.1.2.3 Compatible SMRAM Address Range (A0000h-BFFFFh) .............102 5.1.2.4 Monochrome Adapter (MDA) Range (B0000h - B7FFFh) ............102 5.1.2.5 Expansion Area (C0000h-DFFFFh) ..............................................103 5.1.2.6 Extended System BIOS Area (E0000h-EFFFFh) .........................103 5.1.2.7 System BIOS Area (F0000h-FFFFFh) ..........................................103 5.1.3 Extended Memory Area .............................................................................103 5.1.3.1 Main System SDRAM Address Range (0010_0000h to Top of Main Memory) ........................................................................................103 5.1.3.1.1 15 MB-16 MB Window ................................................104 5.1.3.1.2 Pre-allocated Memory.................................................104 5.1.3.2 Extended SMRAM Address Range (HSEG and TSEG) ...............104 5.1.3.2.1 HSEG ..........................................................................104 5.1.3.2.2 TSEG ..........................................................................104 5.1.3.3 PCI Memory Address Range (Top of Main Memory to 4 GB) ......104 5.1.3.4 Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000hFEEF_FFFFh) ...............................................................................105 5.1.3.5 High BIOS Area (FFE0_0000h -FFFF_FFFFh) ............................105 5.1.4 AGP Memory Address Ranges..................................................................105 5.2 Host Interface...............................................................................................................106 5.2.1 Overview ....................................................................................................106 5.2.2 Intel Pentium III Processor-M Unique PSB Activity ...................................106 5.2.3 Host Addresses Above 4 GB .....................................................................108 5.2.4 Host Bus Cycles.........................................................................................109 5.2.4.1 Partial Reads.................................................................................109 5.2.4.2 Part-Line Read and Write Transactions........................................109 5.2.4.3 Cache Line Reads.........................................................................109 5.2.4.4 Partial Writes.................................................................................109 5.2.4.5 Cache Line Writes.........................................................................109 5.2.4.6 Memory Read and Invalidate (Length > 0) ...................................109 5.2.4.7 Memory Read and Invalidate (Length = 0) ...................................109 5.2.4.8 Memory Read (Length = 0) ...........................................................110 5.2.4.9 Host Initiated Zero-Length R/W Cycles.........................................110 5.2.4.10 Cache Coherency Cycles..............................................................110 5.2.4.11 Interrupt Acknowledge Cycles ......................................................111 5.2.4.12 Locked Cycles ...............................................................................111 5.2.4.12.1 CPU<->System SDRAM Locked Cycles ....................111 5.2.4.12.2 CPU<->Hub Interface Locked Cycles .........................111 5.2.4.12.3 CPU<->AGP/PCI Locked Cycles ................................111 5.2.4.13 Branch Trace Cycles.....................................................................111
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5.5
5.6 5.7
5.2.4.14 Special Cycles .............................................................................. 111 5.2.5 In-Order Queue Pipelining......................................................................... 113 5.2.6 Write Combining........................................................................................ 113 System Memory Interface ........................................................................................... 113 5.3.1 SDRAM Interface Overview ...................................................................... 113 5.3.2 SDRAM Organization and Configuration .................................................. 114 5.3.2.1 Configuration Mechanism for SO-DIMMs..................................... 114 5.3.2.1.1 Memory Detection and Initialization ........................... 114 5.3.2.1.2 SDRAM Register Programming ................................. 115 5.3.3 SDRAM Address Translation and Decoding ............................................. 115 5.3.4 SDRAM Performance Description............................................................. 116 AGP Interface .............................................................................................................. 116 5.4.1 AGP Target Operations............................................................................. 117 5.4.2 AGP Transaction Ordering ........................................................................ 118 5.4.3 AGP Electricals ......................................................................................... 118 5.4.4 Support for PCI-66 Devices....................................................................... 118 5.4.5 4x AGP Protocol........................................................................................ 118 5.4.6 Fast Writes ................................................................................................ 118 5.4.7 AGP-to-Memory Read Coherency Mechanism......................................... 119 5.4.8 PCI Semantic Transactions on AGP ......................................................... 119 5.4.8.1 PCI Read Snoop-Ahead and Buffering ........................................ 119 5.4.8.2 GMCH-M Initiator and Target Operations .................................... 120 5.4.8.3 GMCH-M Retry/Disconnect Conditions ........................................ 122 5.4.8.4 Delayed Transaction..................................................................... 122 GMCH-M Power and Thermal Management............................................................... 123 5.5.1 ACPI 2.0 Support ...................................................................................... 123 5.5.2 ACPI States Supported ............................................................................. 123 5.5.3 Intel 830MP Chipset System and CPU States .......................................... 125 5.5.4 Intel 830MP Chipset CPU "C" States ........................................................ 125 5.5.4.1 Full-On (C0) .................................................................................. 125 5.5.4.2 Auto-Halt (C1)............................................................................... 125 5.5.4.3 Quickstart (C2).............................................................................. 125 5.5.4.4 Deep Sleep (C3) ........................................................................... 126 5.5.5 Intel 830MP Chipset AGP_BUSY# Protocol with External Graphics ........ 126 5.5.6 Intel SpeedStep Technology .................................................................. 126 5.5.7 Intel 830MP Chipset System "S" States.................................................... 127 5.5.7.1 Powered-On-Suspend (POS) (S1) .............................................. 127 5.5.7.2 Suspend-To-RAM (STR) (S3) ...................................................... 127 5.5.7.3 S4 (SUSPEND TO DISK), S5 (Soft Off) State ............................. 127 5.5.8 System Memory Dynamic CKE support.................................................... 127 5.5.9 GMCH-M Thermal Management............................................................... 128 5.5.9.1 System Bandwidth Monitoring and Throttling............................... 128 Clocking....................................................................................................................... 128 XOR Test Chains......................................................................................................... 128 5.7.1.1 Test Mode Entry ........................................................................... 128 5.7.1.2 RAC Chain Initialization ................................................................ 129 5.7.1.3 XOR Chain Test Pattern Consideration for Differential Pairs....... 131 5.7.1.4 XOR Chain Exclusion List ............................................................ 132 5.7.1.5 NC Balls ........................................................................................ 133 5.7.1.6 XOR Chain Connectivity/Ordering................................................ 134
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Performance............................................................................................................................. 146 Mechanical Specification.......................................................................................................... 147
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Intel 830MP Chipset GMCH-M Ballout Diagram..........................................................147 Intel 830MP Chipset GMCH-M Signal List...................................................................150 Intel 830MP Chipset Package Dimensions..................................................................159
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Figures
Figure 1. Intel 830MP Chipset Interface Block Diagram ............................................................ 14 Figure 2. Logical Bus Structure During PCI Configuration ........................................................ 37 Figure 3. Configuration Cycle Flow Chart .................................................................................. 38 Figure 4. Hub Interface Type 0 Configuration Address Translation........................................... 39 Figure 5. Hub Interface Type 1 Configuration Address Translation........................................... 40 Figure 6. Mechanism #1 Type 0 Configuration Address to PCI Address Mapping ................... 40 Figure 7. Mechanism #1 Type 1 Configuration Address to PCI Address Mapping ................... 41 Figure 8. PAM Registers ............................................................................................................ 60 Figure 9. Memory System Address Map.................................................................................. 100 Figure 10. Detailed Memory System Address Map ................................................................. 101 Figure 11. XOR Chain Test Mode Entry Events Diagram ....................................................... 129 Figure 12. RAC Chain Timing Diagram ................................................................................... 130 Figure 13. Intel 830MP Chipset Ballout (Left Side).................................................................. 148 Figure 14. Intel 830MP Chipset Ballout (Right Side) ............................................................... 149 Figure 15. Intel 830MP Chipset GMCH-M Package Dimensions ............................................ 159
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Tables
Table 1. Signal Voltage Levels ...................................................................................................19 Table 2. Host Interface Signal Descriptions ...............................................................................20 Table 3. System Memory Interface Signal Descriptions.............................................................22 Table 4. AGP Addressing Signal Descriptions ...........................................................................23 Table 5. AGP Flow Control Signal Descriptions .........................................................................24 Table 6. AGP Status Signal Descriptions ...................................................................................24 Table 7. AGP Clock Signal-Strobe Descriptions ........................................................................25 Table 8. PCI Signals - AGP Semantics Signal Descriptions .....................................................26 Table 9. Hub Interface Signal Descriptions ................................................................................28 Table 10. Clocking and Reset Signal Descriptions ....................................................................29 Table 11. Graphics Memory Interface Signal Descriptions ........................................................30 Table 12. Dedicated Digital Video Port (DVOA) Signal Descriptions.........................................31 Table 13. Analog Display Signal Descriptions............................................................................32 Table 14. Display Control Signal Descriptions ...........................................................................33 Table 15. Voltage References, PLL Power Signal Descriptions ................................................34 Table 16. Strap Signal Descriptions ...........................................................................................35 Table 17. AGP/PCI1 Config Address Remapping......................................................................41 Table 18. Nomenclature for Access Attributes ...........................................................................45 Table 19. Host-Hub I/F Bridge/SDRAM Controller Configuration Space (Device #0)................46 Table 20. Attribute Bit Assignment .............................................................................................59 Table 21. PAM Registers and Associated Memory Segments ..................................................61 Table 22. Summary of GMCH-M Error Sources, Enables and Status Flags .............................74 Table 23. Host-AGP Bridge Configuration Space (Device #1)...................................................84 Table 24. Memory Segments and Attributes ............................................................................102 Table 25. Host Bus Transactions Supported by GMCH-M.......................................................107 Table 26. Host Bus Responses Supported by GMCH-M .........................................................108 Table 27. GMCH-M Responses to Host Initiated Special Cycles ............................................112 Table 28. System Memory SO-DIMM Configurations ..............................................................114 Table 29. Data Bytes on SO-DIMM Used for Programming SDRAM Registers ......................115 Table 30. Address Translation and Decoding ..........................................................................116 Table 31. AGP Commands Supported by GMCH-M When Acting as an AGP Target ............117 Table 32. PCI Commands Supported by GMCH-M When Acting as a PCI Target .................120 Table 33. PCI Commands Supported by GMCH-M When Acting as an AGP/PCI1 Initiator ...121 Table 34. Intel 830MP Chipset System and CPU States .........................................................125 Table 35. RAC Chain Timing Descriptions ...............................................................................130 Table 36. XOR Chain Differential Pairs ....................................................................................131 Table 37. NC Ball and Associated XOR Chain ........................................................................133 Table 38. XOR Chain AGP1.....................................................................................................134 Table 39. XOR Chain AGP2.....................................................................................................135 Table 40. XOR Chain DVO.......................................................................................................136 Table 41. XOR Chain PSB1 .....................................................................................................136 Table 42. XOR Chain PSB2 .....................................................................................................138 Table 43. XOR Chain GPIO .....................................................................................................140 Table 44. XOR Chain HUB .......................................................................................................140 Table 45. XOR Chain SM1 .......................................................................................................141 Table 46. XOR Chain SM2 .......................................................................................................142 Table 47. XOR Chain CMOS....................................................................................................144 Table 48. XOR Chain RAC .......................................................................................................144 Table 49. System Bandwidths ..................................................................................................146 Table 50. Intel 830MP Chipset Ballout Signal Name List.........................................................150
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Revision History
Rev. 001 Initial Release Description Date July 2001
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Product Features
Mobile Processor/Host Bus Support *Optimized for Mobile Intel(R) Pentium(R) III Processor-M at 133-MHz host bus frequency *Supports 32-bit host bus addressing *1.25V AGTL bus driver technology (gated AGTL receivers for reduced power) *Supports single/dual ended AGTL termination System Memory SDRAM Controller *Single Data Rate (SDR) SDRAM Support Supports PC133 only Four integrated 133- MHz System Memory Clocks Supports 64-Mb, 128-Mb, 256-Mb, and 512-Mb technologies Maximum of 1.0 GB of System Memory using 512-Mb technology Supports LVTTL signaling interface Hub Interface Proprietary interconnect between GMCHM and ICH3-M Accelerated Graphics Port (AGP) Interface Supports a single AGP or PCI-66 device AGP Support Supports AGP 2.0 including 4x AGP data transfers AGP 1.5V Signaling only Fast Writes PCI Support 66-MHz PCI 2.2 Specification compliant with the following exceptions: 1.5V but not 3.3V safe, AGP 2.0 specification electricals Power Management APM Rev 1.2 compliant power management ACPI 1.0b and 2.0 Support System states: S0, S1, S3, S4, S5 CPU states: C0, C1, C2, C3 Package 625 PBGA IO Device Support 82801CAM (I/O Controller Hub)
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Intel 830MP Chipset Interface Block Diagram
Intel(R) (R) Pentium(R) III-M Processor Side Bus
Ext. GC
GMCH-M AGP
System Memory
SDRAM
Hub Interface
USB IDE
ICH3-M
PCI Bus
LAN Docking
Super I/O
LPC I/F
Keyboard, Mouse, PP SP, IR
LPC FLASH
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1.1
Introduction
This document provides the external design specifications for notebook computer manufacturers.
Document References
* Mobile Intel(R) Pentium(R) III Processor-M Datasheet (298340-001) * PCI Local bus Specification 2.2: Contact www.pcisig.com * Intel(R) 82801CAM I/O Controller Hub 3 (ICH3-M) Datasheet (290716-001) * Intel(R) 830MP Chipset Design Guide (298339-001 * Advanced Graphic Port (AGP) 2.0 Specification: Contact ftp://download.intel.com/technology/agp/downloads/agp20.pdf * Advanced Configuration and Power Management (ACPI) Specification 1.0b & 2.0: Contact http://www.teleport.com/~acpi/ * Advanced Power Management (APM) Specification 1.2: Contact http://www.microsoft.com/hwdev/busbios/amp_12.htm * Write Combing Memory Implementation Guideline: Contact http://developer.intel.com/design/PentiumII/applnots/244422.htm * IA-32 Intel Architecture Software Developer Manuel Volume 3: System Programming Guide: Contact http://developer.intel.com/design/Pentium4/manuals/24547203.pdf
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Overview
Figure 1. Intel 830MP Chipset Interface Block Diagram
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2.1
Terminology
GMCH3-MP (GMCH-M) 82801CAM I/O Controller Hub (ICH3-M) Hub Interface The Intel 830MP Graphics and Memory Controller Hub-Mobile component that contains the CPU interface, system SDRAM controller, and AGP interface. It communicates with the ICH3-M over a proprietary interconnect called the hub interface. The ICH3-M is connected to the GMCH-M through a proprietary interconnect called the hub interface. This is the I/O Controller Hub or ICH component that contains the primary PCI interface, LPC interface, USB1.1, ATA-100 and other IO functions. The proprietary interconnect between the GMCH-M and the ICH3-M. In this document hub interface cycles originating from or destined for the ICH3-M are generally referred to as hub interface cycles. Hub cycles originating from or destined for the primary PCI interface on the ICH3-M are sometimes referred to as Hub Interface/PCI cycles. Accelerated Graphics Port. Refers to the AGP/PCI interface that is in the GMCH-M. It supports a 1.5V 66/266 MHz component. PIPE# and SBA cycles are generally referred to as AGP transactions. FRAME# cycles are generally referred to as AGP/PCI transactions. The physical bus that is driven directly by the AGP/PCI1 Bridge (Device #1) in the GMCH-M. This is the primary AGP bus. The primary physical PCI (PCI0) bus that is driven directly by the ICH3-M component. It supports a 3.3V interface and is 5.0V tolerant, 33 MHz PCI 2.2 compliant components. Interaction between PCI0 and GMCH-M occurs over the hub interface. Note that even though the Primary PCI bus is referred to as PCI0 it is not PCI Bus #0 from a configuration standpoint. The secondary physical PCI (PCI1) interface that is a subset of the AGP bus driven directly by the GMCH-M. It supports a subset of 1.5V, 66 MHz PCI 2.2 compliant components. Note that even though the Secondary PCI bus is referred to as PCI1 it may not be configured as PCI Bus #1.
AGP
AGP/PCI1 Primary PCI
Secondary PCI
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System Architecture
The 82830MP Graphics Memory Controller Hub (GMCH-M) is a highly integrated hub that provides the CPU interface (optimized for the mobile Intel(R) Pentium(R) III Processor-M processor), the SDRAM system memory interface, a hub link interface to the 82801CAM I/O Controller Hub (ICH3-M), and is optimized for mobile Intel Pentium III Processor-M configurations at 133-MHz PSB. * 1.25V AGTL host bus supporting 32-bit host addressing * System SDRAM supports PC133 (LVTTL) SDRAM * Supports 1.0 GB of system SDR * AGP interface with 1x/2x/4x SBA/Data Transfer and 2x/4x Fast Write capability * Hub interface to ICH3-M
2.3
Host Interface
The 830MP chipset GMCH-M is optimized for the Intel Pentium III Processor-M. The GMCH-M supports a PSB frequency of 133 MHz using 1.25V AGTL signaling. Single ended/dual ended termination AGTL is supported for single processor configurations. It supports 32-bit host addressing, decoding up to 4 GB of the CPU's memory address space. Host initiated I/O cycles are decoded to AGP/PCI1, Hub interface, or GMCH-M configuration space. Host initiated memory cycles are decoded to AGP/PCI1, Hub interface, or system SDRAM. All memory accesses from the Host interface that hit the graphics aperture are translated using an AGP address translation table. AGP/PCI1 device accesses to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated from AGP/PCI1 using PCI semantics and from Hub interface to system SDRAM will be snooped on the host bus.
2.4
System Memory Interface
The Intel 830MP chipset GMCH-M integrates a system memory SDRAM controller with a 64-bit wide interface. The GMCH-M supports Single Data Rate (SDR) SDRAM for system memory. Consequently, the Intel 830MP chipset's system memory buffers support LVTTL signal interfaces. Configured for Single Data Rate SDRAM, the Intel 830MPchipset's memory interface includes support for the following: * Up to 1.0 GB of 133-MHz SDR SDRAM using 512-Mb technology * PC133 SO-DIMMs * Maximum of two SO-DIMMs, single-sided and/or double-sided * The Intel 830MP chipset only supports four bank memory technologies. * Four Integrated Clock buffers
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AGP Interface
A single AGP or PCI-66 component or connector (not both) is supported by the GMCH-M's AGP interface. Support for a single PCI-66 device is limited to the subset supported by the AGP 2.0 Specification. The AGP/PCI1 buffers operate in 1.5V mode and support the AGP 1.5V Connector: Note: 1.5V drive, not 3.3V safe. This mode is compliant with the AGP 2.0 spec. The AGP/PCI1 interface supports up to 4x AGP signaling and up to 4x Fast Writes. AGP semantic cycles to system SDRAM are not snooped on the host bus. PCI semantic cycles to system SDRAM are snooped on the host bus. The GMCH-M supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. The GMCH-M contains a 32-deep AGP request queue. High priority accesses are supported.
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3
Signal Description
This section provides a detailed description of the Intel 82830MP GMCH-M signals. The signals are arranged in functional groups according to their associated interface. The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name the signal is asserted when at the high voltage level. When not otherwise specified, "set" refers to changing a bit to its asserted state (a logical 1). Clear refers to changing a bit to its negated state (a logical 0). The following notations are used to describe the signal type: The following notations are used to describe the signal type: I O I/O s/t/s as/t/s Input pin Output pin Bi-directional Input/Output pin Sustained Tristate. This pin is driven to its inactive state prior to tri-stating. Active Sustained Tristate. This applies to some of the Hub interface signals. This pin is weekly driven to its last driven value.
The signal description also includes the type of buffer used for the particular signal: AGTL Open Drain 1.25V AGTL interface signal. Refer to the AGTL+ I/O Specification for complete details. AGTL+ signals are "inverted bus" style where a low voltage represents a logical "1". Signals used for AGP or 1.5V interfaces. AGP signals are compatible with AGP 2.0 1.5V Signaling Environment DC and AC Specifications. The buffers are not 3.3V tolerant. Low Voltage TTL compatible signals. These are also 3.3V outputs. CMOS buffers.
AGP/1.5V
LVTTL CMOS
Note that CPU address and data bus signals are logically inverted signals. In other words, the actual values are inverted of what appears on the CPU bus. This must be taken into account and the addresses and data bus signals must be inverted inside the GMCH-M. All CPU control signals follow normal convention. A 0 indicates an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix. Table 1 shows the Vtt/Vdd and Vref levels for the various interfaces.
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Table 1. Signal Voltage Levels
Interface AGTL+ 1.5v/AGP LVTTL RSL (Reserved) Hub Interface Vtt/Vdd (nominal) 1.25V 1.5V 3.3V 1.8V 1.8V Vref 2/3 * Vtt 0.5 * Vdd Vddq * 0.5 1.4V 0.5 * Vdd
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Host Interface Signals
Signal Name CPURST# Type O AGTL+ Description CPU Reset. The CPURST# pin is an output from the GMCH-M. The GMCH-M asserts CPURST# while RESET# (PCIRST# from ICH3-M) is asserted and for approximately 1 ms after RESET# is deasserted. The CPURST# allows the CPUs to begin execution in a known state. Note that the ICH3-M must provide CPU strap set-up and hold times around CPURST#. This requires strict synchronization between GMCH-M CPURST# deassertion and ICH3-M driving the straps. HA[31:3]# I/O AGTL+ Host Address Bus: HA[31:3]# connect to the CPU address bus. During CPU cycles the HA[31:3]# are inputs. The GMCH-M drives HA[31:3]# during snoop cycles on behalf of hub interface and AGP/Secondary PCI initiators. Note that the address bus is inverted on the CPU bus. Host Data: These signals are connected to the CPU data bus. Note that the data signals are inverted on the CPU bus. Address Strobe: The CPU bus owner asserts ADS# to indicate the first of two cycles of a request phase. Block Next Request: Used to block the current request bus owner from issuing a new request. This signal is used to dynamically control the CPU bus pipeline depth. Priority Agent Bus Request: The GMCH-M is the only Priority Agent on the CPU bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Data Bus Busy: Used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer: GMCH-M will generate a deferred response as defined by the rules of the GMCH-M's dynamic defer policy. The GMCH-M will also use the DEFER# signal to indicate a CPU retry response. Data Ready: Asserted for each cycle that data is transferred.
Table 2. Host Interface Signal Descriptions
HD[63:0]#
I/O AGTL+
ADS#
I/O AGTL+
BNR#
I/O AGTL+
BPRI#
O AGTL+
DBSY#
I/O AGTL+
DEFER#
O AGTL+
DRDY#
I/O AGTL+
HIT#
I/O AGTL+
Hit: Indicates that a caching agent holds an unmodified version of the requested line. Also, driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: Indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. Also, driven in conjunction with HIT# to extend the snoop window. Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic, i.e. no hub interface or AGP/PCI snoopable access to SDRAM is allowed when HLOCK# is asserted by the CPU. Host Request Command: Asserted during both clocks of request phase. In the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type. The transactions supported by the GMCH-M Host Bridge are defined in the Host
HITM#
I/O AGTL+
HLOCK#
I AGTL+
HREQ[4:0]#
I/O AGTL+
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Interface section of this document. HTRDY# I/O AGTL+ RS[2:0]# I/O AGTL+ Host Target Ready: Indicates that the target of the CPU transaction is able to enter the data transfer phase. Response Signals: Indicates type of response according to the following table: RS[2:0] 000 001 010 011 100 101 110 111 GTL_RCOMP I/O Response type Idle state Retry response Deferred response Reserved (not driven by GMCH-M) Hard Failure (not driven by GMCH-M) No data response Implicit Writeback Normal data response
GTL Compensation: Used to calibrate the GTL interface buffers to match the board. This pin should be connected to an 80- simple resistor to ground.
Total pins for this section: 113.
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System Memory Interface
Signal Name SM_MA[12:0] Type O LVTTL SM_BA[1:0] O LVTTL SM_MD[63:0] I/O LVTTL SM_DQM[7:0] O LVTTL SM_CS[3:0]# OLVTTL Input/Output Data Mask: These pins act as synchronized output enables during read cycles and as byte enables during write cycles. Chip Select: For the memory rows configured with SDRAM, these pins perform the function of selecting the particular SDRAM components during the active state. Note: There is one SM_CS per SDRAM row. These signals can be toggled on every rising System Memory Clock edge. SDRAM Row Address Strobe: A table of the SDRAM commands supported by 830MP is given in the SDRAM section. SM_RAS# may be heavily loaded and requires 2 SDRAM clock cycles for setup time to the SDRAMs. SDRAM Column Address Strobe: A table of the SDRAM commands supported by 830MP is given in the SDRAM section. SM_CAS# may be heavily loaded and requires 2 SDRAM clock cycles for setup time to the SDRAMs. Write Enable Signal: SM_WE# is asserted during writes to SDRAM. Refer to truth table of the SDRAM commands supported by 830MP, given in the SDRAM section. SM_WE# may be heavily loaded and requires 2 SDRAM clock cycles for setup time to the SDRAMs. Clock Enable: These signals are used to signal a self refresh or power down command to a SDRAM array when entering system suspend. SM_CKE is also used to dynamically power down inactive SDRAM rows. There is one SM_CKE per SDRAM row. These signals can be toggled on every rising SM_CLK Clock edge. System Memory Output Clock: This signal delivers a synchronized clock to the SM_RCLK pin. System Memory Return Clock: This signal receives the synchronized clock from SM_OCLK. System Memory Clock: These signals deliver a synchronized clock to the SDRAMs. System Memory RCOMP: Used to calibrate the system memory I/O buffers. This pin should be connected to a 27.5- resistor tied to Vss. Description Memory Address: SM_MA[12:0] are used to provide the multiplexed row and column address to SDRAM. Memory Bank Address: These signals define the banks that are selected within each SDRAM row. The SM_MAn and SM_BA signals combine to address every possible location within a SDRAM device. Memory Data: These signals are used to interface to the SDRAM data bus.
Table 3. System Memory Interface Signal Descriptions
SM_RAS#
O LVTTL
SM_CAS#
O LVTTL
SM_WE#
O LVTTL
SM_CKE[3:0]
O LVTTL
SM_OCLK
O LVTTL
SM_RCLK
I LVTTL
SM_CLK [3:0]
O LVTTL
SM_RCOMP
I/O
Total pins for System Memory Section: 105.
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3.3.1
AGP Interface Signals
AGP Addressing Signals
Signal Name PIPE# Type I AGP Description Pipelined Read: This signal is asserted by the current master to indicate a full width address is to be queued by the target. The master queues one request each rising clock edge while PIPE# is asserted. When PIPE# is deasserted no new requests are queued across the AD bus. PIPE# is a sustained tri-state signal from the master (graphics controller) and is an input to the GMCH-M. Sideband Address: This bus provides an additional bus to pass address and command to the GMCH-M from the AGP master.
Table 4. AGP Addressing Signal Descriptions
SBA[7:0]
I AGP
The above table contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. When PIPE# is used to queue addresses, the master is not allowed to queue addresses using the SBA bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset.
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AGP Flow Control Signals
Signal Name RBF# Type I AGP Description Read Buffer Full: Indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted the GMCH-M is not allowed to return low priority read data to the AGP master on the first block. RBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data then it is not required to implement this signal. Write Buffer Full: Indicates if the master is ready to accept fast write data from the GMCH-M. When WBF# is asserted the GMCH-M is not allowed to drive fast write data to the AGP master. WBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept fast write data then it is not required to implement this signal.
Table 5. AGP Flow Control Signal Descriptions
WBF#
I AGP
3.3.3
AGP Status Signals
Signal Name ST[2:0] Type O AGP Description Status: Provides information from the arbiter to the AGP Master on what it may do. ST[2:0] only have meaning to the master when its GNT# is asserted. When GNT# is deasserted these signals have no meaning and must be ignored. 000 001 010 011 100 101 110 111 Indicates that previously requested low priority read data is being returned. Indicates that previously requested high priority read data is being returned. Indicates that the master is to provide low priority write data for a previously queued write command. Indicates that the master is to provide high priority write data for a previously queued write command. Reserved Reserved Reserved Indicates that the master has been given permission to start a bus transaction. The master may queue AGP requests by asserting PIPE# or start a PCI transaction by asserting FRAME#. ST[2:0] are always an output from the GMCH-M and an input to the master.
Table 6. AGP Status Signal Descriptions
AGP_BUSY#
OLVTTL
AGP_BUSY#: Output of the GMCH-M graphics controller to the ICH3-M, which indicates that certain graphics activity is taking place. It will indicate to the ACPI software to not enter the C3 state. It will also cause a C3 exit if C3 was being entered, or was already entered when AGP_BUSY# went active. AGP_BUSY# will be inactive when the graphics controller is in any ACPI state other than D0. AGP RCOMP: Used to calibrate AGP I/O buffers. This signal has an external 55 pull-down resistor.
AGP_RCOMP
I/O
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AGP Clocking Signals - Strobes
Signal Name AD_STB0 Type I/O (s/t/s) AGP AD_STB0# I/O (s/t/s) AGP AD_STB1 I/O (s/t/s) AGP AD_STB1# I/O (s/t/s) AGP SB_STB I AGP SB_STB# I AGP Sideband Strobe: Provides timing for 2x and 4x clocked data on the SBA[7:0] bus. The AGP master drives it after the system has been configured for 2x or 4x clocked sideband address delivery. Sideband Strobe Complement: The differential complement to the SB_STB signal. It is used to provide timing for 4x clocked data. AD Bus Strobe-1 Complement: The differential complement to the AD_STB1 signal. It is used to provide timing for 4x clocked data. AD Bus Strobe-1: Provides timing for 2x and 4x clocked data on AD[31:16] and C/BE[3:2]#. The agent that is providing data drives this signal. AD Bus Strobe-0 Complement: The differential complement to the AD_STB0 signal. It is used to provide timing for 4x clocked data. Description AD Bus Strobe-0: Provides timing for 2x and 4x clocked data on AD[15:0] and C/BE[1:0]#. The agent that is providing data drives this signal.
Table 7. AGP Clock Signal-Strobe Descriptions
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PCI Signals - AGP Semantics
PCI signals are redefined when used in AGP transactions that are carried using AGP protocol extension. For transactions on the AGP interface that are carried using PCI protocol, these signals completely preserve PCI 2.2 semantics. The exact roles of all PCI signals during AGP transactions are defined below.
Table 8. PCI Signals - AGP Semantics Signal Descriptions
Signal Name G_FRAME# Type I/O s/t/s AGP G_IRDY# I/O s/t/s AGP G_IRDY# indicates the AGP compliant master is ready to provide all write data for the current transaction. Once IRDY# is asserted for a write operation, the master is not allowed to insert wait states. The assertion of IRDY# for reads indicates that the master is ready to transfer to a subsequent block (32 bytes) of read data. The master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a read transaction. However, it may insert wait states after each 32 byte block is transferred. (There is no G_FRAME# -- G_IRDY# relationship for AGP transactions.) For Fast Write transactions, G_IRDY# is driven by the GMCH-M to indicate when the write data is valid on the bus. The GMCH-M deasserts this signal to insert wait states on block boundaries. G_TRDY# I/O s/t/s AGP G_TRDY# indicates the AGP compliant target is ready to provide read data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert wait states after each block (32 bytes) is transferred on both read and write transactions. For Fast Write transactions the AGP master uses this signal to indicate if and when it is willing to transfer a subsequent block. G_STOP# I/O s/t/s AGP G_DEVSEL# I/O s/t/s AGP G_REQ# I AGP G_GNT# O AGP G_GNT# Same meaning as PCI but additional information is provided on ST[2:0]. The additional information indicates that the selected master is the recipient of previously requested read data (high or normal priority), it is to provide write data (high or normal priority), for a previously queued write command or has been given permission to start a bus transaction (AGP or PCI). G_AD[31:0] Same as PCI. G_STOP# Not used during an AGP transaction. For Fast Write transactions G_STOP# is used to signal Disconnect or Target Abort terminations. G_DEVSEL# Not used during an AGP transaction. For Fast Write transactions it is used when the transaction cannot complete during the block. G_REQ# (Used to request access to the bus to initiate a PCI or AGP request.) Description Not used during an AGP pipelined transaction. G_FRAME# is an output from the GMCH-M during Fast Writes.
G_AD[31:0]
I/O AGP
G_C/BE[3:0]#
I/O AGP
G_C/BE[3:0]# Slightly different meaning. Provides command information (different commands than PCI) when requests are being queued when using PIPE#. Provide valid byte information during AGP write transactions and are not
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used during the return of read data. G_PAR I/O AGP G_PAR Same as PCI. Not used on AGP transactions but used during PCI transactions as defined by the PCI specification.
NOTES: 1. PCIRST# from the ICH3-M is connected to RESET# and is used to reset AGP interface logic within the GMCHM. The AGP agent will also use PCIRST# provided by the as an input to reset its internal logic. 2. LOCK# signal is not supported on the AGP interface (even for PCI operations). 3. The SERR# and PERR# signals are not supported on the AGP interface.
Total pins for AGP section: 66.
3.3.6
PCI Pins During PCI Transactions on AGP Interface
PCI signals described in a previous table behave according to PCI 2.2 specifications when used to perform PCI transactions on the AGP Interface.
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Hub Interface Signals
Signal Name HL[10:0] Type I/O (as/t/s) CMOS HLSTRB; HLSTRB# I/O (as/t/s) CMOS HL_RCOMP I/O HL_RCOMP Hub Interface Compensation: Used to calibrate the hub I/O buffers. This signal has an external 55 ohm pull-down resistor. HLSTRB; HLSTRB# Hub Interface Strobe/Complement. The two differential strobe signals used to transmit or receive packet data. Description HL[10:0] Hub Interface Signals. Signals used for the hub interface.
Table 9. Hub Interface Signal Descriptions
Total pins for this section: 14.
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Clocking and Reset
Signal Name HTCLK; HTCLK# GBOUT Type I CMOS O CMOS GBIN I CMOS GM_GCLK; GM_RCLK DCLKREF O CMOS I LVTTL RESET# I LVTTL Reset In: When asserted, this signal will asynchronously reset the GMCH-M logic. This signal is connected to the PCIRST# output of the ICH3-M. The ICH3-M drives this to 3.3V. All AGP/PCI output and bi-directional signals will also tri-state compliant to PCI rev 2.2 specifications. This input should have a Schmidt trigger to avoid spurious resets. Note that this input needs to be 3.3-V tolerant. Reserved Description Host Clock In: These pins receive a buffered host clock from the external clock synthesizer. This clock is used by all of the GMCH-M. The clock is also the reference clock for the graphics core PLL. This is a low voltage differential input. AGP/Hub Clock Reference Output: This clock goes to the external AGP/Hub/PCI buffer. AGP/Hub Input Clock: 66 MHz, 3.3-V input clock from external buffer AGP/Hub-link interface. Reserved
Table 10. Clocking and Reset Signal Descriptions
Total pins for Clocks/Resets section: 8.
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3.6.1
Intel 830MP Reserve Signals
Graphics Memory Interface
Signal Name DQ_A[7:0] Type I/O RSL DQ_B[7:0] I/O RSL RQ[7:0] O RSL CTM;CTM# I RSL CFM;CFM# O RSL CMD O CMOS SCK O CMOS SIO I/O CMOS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved
Table 11. Graphics Memory Interface Signal Descriptions
Total pins for Graphics Direct RDRAM Section: 31.
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Dedicated Digital Video Port (DVOA)
Signal Name DVOA_CLK; DVOA_CLK# DVOA_D[11:0] Type O 1.5V O 1.5V DVOA_HSYNC O 1.5V DVOA_VSYNC O 1.5V DVOA_BLANK# O 1.5V DVOA_RCOMP DVOA_INTR# I/O I 1.5V DVOA_CLKINT I 1.5V DVOA_FLD/STL I 1.5V Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved
Table 12. Dedicated Digital Video Port (DVOA) Signal Descriptions
Total pins for DVOA section: 21.
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Analog Display
Pin Name VSYNC Type O LVTTL HSYNC O LVTTL RED O Analog GREEN O Analog BLUE O Analog REFSET I NA RED# O Analog GREEN# O Analog BLUE# O Analog Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved
Table 13. Analog Display Signal Descriptions
Total pins for Display section: 9.
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Display Control Signals
Pin Name DDC1_CLK Type I/O LVTTL DDC1_DATA I/O LVTTL I2C_CLK I/O LVTTL I2C_DATA I/O LVTTL DDC2_CLK I/O LVTTL DDC2_DATA I/O LVTTL Reserved Reserved Reserved Reserved Reserved Description Reserved
Table 14. Display Control Signal Descriptions
Total pins for this section: 6
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Voltage References, PLL Power
Signal Name GTL_REF[B:A] Number 2 Description GTL Reference: Reference voltage input for the Host AGTL interface. GTLREF is 2/3 * VTT. VTT is nominally 1.25V. VTT AGPREF 9 1 Host Voltage: VTT is nominally 1.25V for host signals. AGP Reference: Reference voltage input for the AGP interface. AGPREF is 0.5 * Vagpdd when Vdd=1.5V. VCC_AGP VCCQ_AGP HLREF 8 2 1 AGP Voltage: VDD is nominally 1.5V for AGP. AGP Quiet Voltage: Quiet voltage for AGP interface is also 1.5V. Hub Interface Reference: Reference voltage input for the hub interface. HLREF is 0.5 * Vdd. VCC_HUB SM_REF[B:A] VCC_SM VCCQ_SM VCC_GPIO VCC_DVO VCCA_DAC; VSSA_DAC RAM_REF[B:A] VCC_CMOS; VSS_CMOS VCC_LM VDD_LM VCCA_CPLL; VSSA_CPLL VCCA_HPLL; VSSA_HPLL VCCA_DPLL[1:0]; VSSA_DPLL[1:0] VCC VSS 11 22 24 140 2 2 14 5 2 3 21 Hub Interface Voltage: VCC supplies for the hub interface are 1.8V. System Memory Reference: Reference voltage input for system memory is VCC_SM/6 = .55V. System Memory Voltage: VCC supplies for system memory are 3.3V. System Memory Quiet Voltage: Quiet VCC for the system memory interface is 3.3V. GPIO Voltage: VCC supplies for general purpose I/O signals are 3.3V. DVO Voltage: VCC supplies for digital video output signals are 1.5V. DAC Voltage: VCCA and VSSA supplies for the DAC. VCCA_DAC is 1.8V. 2 43 9 7 11 Rambus Reference: Reference voltage input for the Rambus RSL interface. RAMREF is approximately 1.4V Graphics Memory CMOS Voltage: VCC and VSS supplies for local memory CMOS signals. VCC_CMOS is 1.8V VCC Graphics Memory Voltage: VCC supplies for local memory. VCC_LM is 1.8V. VDD Graphics Memory Voltage: VDD supplies for local memory. VDD_LM is 1.25V. (Reserved) Gfx Core PLL Voltage: VCCA and VSSA supplies for core PLL. VCCA_CPLL is 1.25v. Host/Memory/Hub/AGP PLL Voltage: VCCA and VSSA supplies for host PLL. VCCA_HPLL is 1.25V. Display PLL Voltage: VCCA and VSSA supplies for display PLL. VCCA_DPLL is 1.25V. Core VCC: 1.25V. Ground pins.
Table 15. Voltage References, PLL Power Signal Descriptions
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Strap Signals
Table 16 indicates the strap options invoked by various Intel 830MP chipset GMCH-M signal pins.
Table 16. Strap Signal Descriptions
Signal Name DVOA_D [5] Description Desktop/Mobile Selection. The state of this pin on the rising edge of RESET# selects whether the GMCH-M is desktop or mobile. DVOA_D [5] Desktop/Mobile Part 0 = Desktop Part (Default) 1= Mobile Part DVOA_D[7] XOR Chain. Pulling this pin high on the rising edge of RESET# invokes the XOR Chain test mode for checking the IO buffer connectivity. For normal operation this pin should stay low during the rising edge of RESET#. (Default = 0) To invoke this strap, use an external pull-up resistor to 1.5V. All Z. Pulling this pin high on the rising edge of RESET# tri-states all GMCH outputs when ICH3M is in XOR Chain mode. For normal operation this pin should stay low during the rising edge of RESET#. (Default = 0) To invoke this strap, use an external pull-up resistor to 1.5V.
DVOA_D[8]
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4.1
Register Description
This section details register access and provides PCI register address maps.
Conceptual Overview of the Platform Configuration Structure
The Intel 830MP chipset GMCH-M and the ICH3-M are physically connected with the Hub interface. From a configuration standpoint the Hub interface connecting the GMCH-M and the ICH3-M is logically PCI bus #0. All devices internal to the GMCH-M and ICH3-M appear to be on PCI bus #0. The system's primary PCI expansion bus is physically attached to the ICH3-M and, from a configuration standpoint appears as a hierarchical PCI bus behind a PCI-to-PCI bridge. The primary PCI expansion bus connected to the ICH3-M has a programmable PCI Bus number. Note that even though the primary PCI bus is referred to as PCI0 in this document it is not PCI bus #0 from a configuration standpoint. The GMCH-M contains two PCI devices within a single physical component. The configuration registers for Device 0 and 1 are mapped as devices residing on PCI bus #0. * Device 0: Host-Hub Interface Bridge/SDRAM Controller. Logically, this appears as a PCI device residing on PCI bus #0. Physically, Device 0 contains the standard PCI registers, AGP capabilities registers, SDRAM registers, the Graphics Aperture controller, and other GMCH-M specific registers. * Device 1: Host-AGP Bridge. Logically, this appears as a "virtual" PCI-to-PCI bridge residing on PCI bus #0. Physically, Device 1 contains the standard PCI-to-PCI bridge registers and the standard AGP/PCI1 configuration registers (including the AGP I/O and memory address mapping). Logically the ICH3-M appears as two PCI devices within a single physical component also residing on PCI bus #0. One of the ICH3-M devices residing on PCI Bus #0 is a PCI-to-PCI bridge. Logically, the primary side of the bridge resides on PCI bus #0 while the secondary side is the standard PCI expansion bus (PCI0). Also within the ICH3-M is another PCI Device, the LAN Controller, which resides on the standard PCI expansion bus (PCI0) down from the PCI-to-PCI bridge. Note that a physical PCI bus #0 does not exist and that Hub Interface and the internal devices in the GMCH-M and ICH3-M logically constitute PCI Bus #0 to configuration software. This is shown in Figure 2.
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Figure 2. Logical Bus Structure During PCI Configuration
82830MP GMCH-M
AGP/PCI1 AGP Bridge Device #1
Hub I/F Bridge DRAM Controller Device #0
PCI Bus #0
Hub Interface
LPC Bridge Device #31
PCI Bridge Device #30
PCI0
ICH3-M
LAN Controller Device #8
4.2
Routing Configuration Accesses to PCI0 or AGP/PCI
The GMCH-M supports two bus interfaces: Hub Interface and AGP/PCI. PCI configuration cycles are selectively routed to both interfaces. The GMCH-M is responsible for routing PCI configuration cycles to the proper interface. PCI configuration cycles to ICH3-M internal devices and Primary PCI (including downstream devices) are routed to the ICH3-M via Hub Interface. AGP/PCI1 configuration cycles are routed to AGP. The AGP/PCI1 interface is treated as a separate PCI bus from the configuration point of view. Routing of configuration accesses to AGP/PCI1 is controlled via the standard PCI-PCI bridge mechanism using information contained within the PRIMARY BUS NUMBER, the SECONDARY BUS NUMBER, and the SUBORDINATE BUS NUMBER registers of the Host-AGP/PCI1 (device #1).
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Intel 82830MP GMCH-M Configuration Cycle Flow Charts
Figure 3. Configuration Cycle Flow Chart
DW I/O Write to CONFIG_ADDRESS with bit 31=1
I/O Read/Write to CONFIG_DATA
BUS#=0 Yes No DEV#=0, FN#=0 Yes GMCH-M Claims Bus #0 / Device #0 / Function #0
GMCH-M Generates Type 0 Access to AGP/PCI1
Yes
BUS#= SECONDARY BUS in GMCH-M Dev #1
No
DEV#=1, FN#=0
Yes
GMCH-M Claims Bus #0 / Device #1 / Function #0
No
GMCH-M Generates Type 1 Access to AGP/PCI1
Yes
BUS# > SEC BUS BUS# <= SUB BUS
No
No
GMCH-M Generates hub I/F Type 1 Configuration Cycle
GMCH-M Generates hub I/F Type 0 Configuration Cycle
A detailed description of the mechanism for translating CPU I/O bus cycles to configuration cycles on one of the two buses is described in Figure 3 above.
4.2.2
PCI Bus Configuration Mechanism
The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256, 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the CPU. Configuration space is supported by a mapping mechanism implemented within the GMCH-M. The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The GMCH-M supports only Mechanism #1 for PCI configuration accesses. The configuration access mechanism makes use of the CONFIG_ADDRESS Register and CONFIG_DATA Register. To reference a configuration register, a Dword I/O write cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration cycle. CONFIG_DATA then becomes a
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window into the four bytes of configuration space specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the GMCH-M translating the CONFIG_ADDRESS into the appropriate configuration cycle. The GMCH-M is responsible for translating and routing the CPU's I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH-M configuration registers, Hub Interface, or AGP/PCI1.
4.2.3
PCI Bus #0 Configuration Mechanism
The GMCH-M decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration cycle is targeting a PCI Bus #0 device. The Host-Hub Interface Bridge entity within the GMCH-M is hardwired as Device #0 on PCI Bus #0. The Host-AGP/PCI1 Bridge entity within the GMCH-M is hardwired as Device #1 on PCI Bus #0. Configuration cycles to any of the GMCH-M's internal devices are confined to the GMCH-M and not sent over Hub Interface. Accesses to devices #3 to #31 will be forwarded over Hub Interface as Type 0 Configuration Cycles (see Hub Interface spec). A[1:0] of the Hub Interface Request Packet for the Type 0 configuration cycle will be "00". Bits 15:2 of the CONFIG_ADDRESS register will be translated to the A[15:2] field of the Hub Interface Request Packet of the configuration cycle as shown the figure below. The ICH3-M decodes the Type 0 access and generates a configuration access to the selected internal device.
Figure 4. Hub Interface Type 0 Configuration Address Translation
CONFIG_ADDRESS
Reserved 0 Device Number Function No. Register Number x
31 1
0 x
Hub Interface Type 0 Configuration Address Extension
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15 Device Number Function No. Reserved 31 Register Number
0
00
16
Type 0
4.2.4
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value programmed into the GMCH-M's device #1 SECONDARY BUS NUMBER register or greater than the value programmed into the SUBORDINATE BUS NUMBER Register, the GMCH-M will generate a Type 1 Hub Interface Configuration Cycle. A[1:0] of the Hub Interface Request Packet for the Type 1 configuration cycle will be "01". Bits 31:2 of the CONFIG_ADDRESS register will be translated to the A[31:2] field of the Hub Interface Request Packet of the configuration cycle as shown in the figure below. The ICH3-M compares the non-zero Bus Number with the SECONDARY BUS NUMBER and SUBORDINATE BUS NUMBER registers of its P2P bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH3-M's Hub Interfaces, or a downstream PCI bus.
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Figure 5. Hub Interface Type 1 Configuration Address Translation
31 1 Reserved
CONFIG_ADDRESS
Bus Number Device Number Function No. Register Number x
0 x
Hub Interface Type 1 Configuration Address Extension
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15 Device Number Reserved 31 Function No. Register Number Bus Number
0
01
16
Type 1
4.2.5
AGP/PCI1 Bus Configuration Mechanism
From the chipset configuration perspective, AGP/PCI1 is seen as another PCI bus interface residing on a Secondary Bus side of the "virtual" PCI-PCI bridge referred to as the GMCH-M Host-AGP/PCI1 bridge. On the Primary bus side, the "virtual" PCI-PCI Bridge is attached to PCI Bus #0. Therefore, the PRIMARY BUS NUMBER register is hardwired to "0". The "virtual" PCI-PCI bridge entity converts Type #1 PCI Bus Configuration cycles on PCI Bus #0 into Type 0 or Type 1 configuration cycles on the AGP/PCI1 interface. Type 1 configuration cycles on PCI Bus #0 that have a BUS NUMBER that matches the SECONDARY BUS NUMBER of the GMCH-M's "virtual" PCI-PCI Bridge will be translated into Type 0 configuration cycles on the AGP/PCI1 interface. The GMCH-M will decode the Device Number field [15:11] and assert the appropriate GAD signal as an IDSEL in accordance with the PCI-to-PCI Bridge Type 0 configuration mechanism. For PCI-to-PCI Bridge translation one of 16 IDSELs are generated (as opposed to one of 21 for Host-to-PCI bridges). When bit [15] = 0, bits [14:11] are decoded to assert a single AD[31:16] IDSEL. If bit [15] = 1, AD[31:16] are 0000h. The remaining address bits will be mapped as described in the figure below. The remaining address bits will be mapped as described in the Figure 6 below.
Figure 6. Mechanism #1 Type 0 Configuration Address to PCI Address Mapping
CONFIG_ADDRESS
31 1 Reserved 24 23 Bus Number 16 15 14 11 10 8 7 Register Number 2 1 x 0 x Device Number Function No.
31
24
23
16 15 Reserved = 0
11
10
8
7 Register Number
2
1 0
0 0
IDSEL
Function No.
AGP GAD[31:0] Address
AGP/PCI1 Type 0 Configuration Cycle
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Table 17. AGP/PCI1 Config Address Remapping
Config Address AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 1xxxx AGP GAD[31:16] IDSEL 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000
If the Bus Number is non-zero, greater than the value programmed into the SECONDARY BUS NUMBER register and less than or equal to the value programmed into the SUBORDINATE BUS NUMBER register, the configuration cycle is targeting a PCI bus downstream of AGP/PCI1. The GMCH-M will generate a Type 1 PCI configuration cycle on AGP/PCI1. The address bits will be mapped as described in figure below.
Figure 7. Mechanism #1 Type 1 Configuration Address to PCI Address Mapping
CONFIG_ADDRESS
24 23 87 21 0 16 15 31 30 11 10 1 Reserved Bus Number Device Number Function Number Reg. Index X X
PCI Address AD[31:0] 31
0
Bus Number Device Number Function Number 24 23
16 15
11 10
87
Reg. Index 0 1 21 0
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To prepare for mapping of the configuration cycles on AGP/PCI1 the initialization software will go through the following sequence: Scan all devices residing on the PCI Bus #0 using Type 0 configuration accesses. For every device residing at bus #0 which implements PCI-PCI bridge functionality, it will configure the secondary bus of the bridge with the appropriate number and scan further down the hierarchy. This process will include the configuration of the "virtual" PCI-PCI Bridge within the GMCH-M used to map the AGP address space in a software specific manner. Note: Although initial AGP platform implementations will not support hierarchical buses residing below AGP, this specification still must define this capability in order to support PCI-66 compatibility. Note also that future implementations of the AGP devices may support hierarchical PCI or AGP-like buses coming out of the root AGP device.
4.2.6
Internal GMCH-M Configuration Register Access Mechanism
Accesses decoded as PCI Bus #0/Device #0 (Host-Hub Interface Bridge/SDRAM Controller) or PCI Bus #0/Device #1 (Host-AGP Bridge) are sequenced as Type 0 PCI Configuration Cycle accesses on Bus #0 to Device #0/Function #0, Device #1/Function #0. Note that since GMCH-M device #0 and #1 are not multi-function devices, the function number should always be `0'. If the function number is not `0' for accesses to Device #0 or #1, the GMCH-M will not claim the configuration cycle and it will be forwarded to the Hub Interface where it should be master aborted (by the ICH3-M) in the same way as transactions to other unimplemented PCI configuration targets.
4.3
GMCH-M Register Introduction
The GMCH-M contains two sets of software accessible registers, accessed via the Host CPU I/O address space: 1. 2. Control registers I/O mapped into the CPU I/O space, which control access to PCI and AGP configuration space (see section entitled I/O Mapped Registers). Internal configuration registers residing within the GMCH-M that are partitioned into two logical device register sets ("logical" since they reside within a single physical device). The first register set is dedicated to Host-Hub Interface Bridge functionality (controls PCI Bus #0 i.e. SDRAM configuration, other chip-set operating parameters and optional features). The second register block is dedicated to Host-AGP/PCI1 Bridge functions (controls AGP/PCI1 interface configurations and operating parameters).
Note:
This configuration scheme is necessary to accommodate the existing and future software configuration model supported by Microsoft* where the Host Bridge functionality will be supported and controlled via a dedicated specific driver. Virtual PCI-PCI Bridge functionality will be supported via standard PCI bus enumeration configuration software. The term "virtual" is used to designate that no real physical embodiment of the PCI-PCI Bridge functionality exists within the GMCH-M, but that GMCH-M's internal configuration register sets are organized in this particular manner to create that impression to the standard configuration software. The GMCH-M supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism #1 in the PCI specification. The GMCH-M internal registers (both I/O Mapped and Configuration registers) are accessible by the Host CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS that can only be accessed as a Dword. All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field).
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Some of the GMCH-M registers described in this section contain reserved bits. These bits are labeled "Reserved". Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, and write operations for the configuration address register. In addition to reserved bits within a register, the GMCH-M contains address locations in the configuration space of the Host-Hub Interface Bridge entity that are marked either "Reserved" or "Intel Reserved". The GMCH-M responds to accesses to "Reserved" address locations by completing the host cycle. When a "Reserved" register location is read, a zero value is returned. ("Reserved" registers can be 8-, 16-, or 32-bit in size). Writes to "Reserved" registers have no effect on the GMCH-M. Registers that are marked as "Intel Reserved" must not be modified by system software. Writes to "Intel Reserved" registers may cause system failure. Reads to "Intel Reserved" registers may return a non-zero value. Upon Reset, the GMCH-M sets all of its internal configuration registers to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the SDRAM configurations, operating parameters and optional system features that are applicable, and to program the GMCH-M registers accordingly.
4.4
I/O Mapped Registers
The GMCH-M contains a set of registers that reside in the CPU I/O address space - the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window.
4.4.1
CONFIG_ADDRESS - Configuration Address Register
I/O Address: Default Value: Access: Size: 0CF8h Accessed as a Dword 00000000h Read/Write 32 bits
CONFIG_ADDRESS is a 32-bit register accessed only when referenced as a Dword. A Byte or Word reference will "pass through" the Configuration Address Register and Hub Interface onto the PCI0 bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended.
31 30
0 R 24 23 0 16 15 0 11 10 0 87 0 2 10 R
Bit Default
Reserved Register Number Function Number Device Number Bus Number Reserved Enable
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Bit 31 30:24 23:16
Descriptions Configuration Enable (CFGE). When this bit is set to 1, accesses to PCI configuration space are enabled. If this bit is reset to 0, accesses to PCI configuration space are disabled. Reserved (These bits are read only and have a value of 0). Bus Number. When the Bus Number is programmed to 00h the target of the Configuration Cycle is either the GMCH-M or the ICH3-M. The Configuration Cycle is forwarded to hub interface if the Bus Number is programmed to 00h and no device internal to the GMCH-M is the target. If the Bus Number is non-zero and matches the value programmed into the SECONDARY BUS NUMBER Register of the AGP/PCI1 bridge, a Type 0 PCI configuration cycle will be generated on AGP/PCI1. If the Bus Number is non-zero, greater than the value in the SECONDARY BUS NUMBER register of the AGP/PCI1 bridge, and less than or equal to the value programmed into the SUBORDINATE BUS NUMBER Register, a Type 1 PCI configuration cycle will be generated on AGP/PCI1. If the Bus Number is non-zero, and is less than the value programmed into the SECONDARY BUS NUMBER Register of the AGP/PCI1 bridge, or is greater than the value programmed into the SUBORDINATE BUS NUMBER Register, a Type 1 hub interface Configuration Cycle is generated. Device Number. This field selects one agent on the PCI bus selected by the Bus Number. When the Bus Number field is "00" the GMCH-M decodes the Device Number field. The GMCH-M is always Device #0 for the Host-hub interface bridge entity, and Device #1 for the Host-AGP/PCI1 entity. Therefore, when the Bus Number = 0 and the Device Number = 0, 1, the internal GMCH-M devices are selected. If the Bus Number is non-zero and matches the value programmed into the SECONDARY BUS NUMBER Register of the AGP/PCI1 bridge, a Type 0 PCI configuration cycle will be generated on AGP/PCI1. The Device Number field is decoded and the GMCH-M asserts one and only one GADxx signal as an IDSEL. GAD11 is asserted to access Device #0, GAD12 for Device #1, and so forth up to Device #20 for which will assert GAD31. All device numbers higher than 20 cause a type 0 configuration access with no IDSEL asserted, which will result in a Master Abort reported in the GMCH-M's "virtual" PCI-PCI bridge registers. For Bus Numbers resulting in AGP/PCI1 Type 1 Configuration cycles the Device Number is propagated as GAD[15:11]. Function Number. This field is mapped to GAD[10:8] during AGP/PCI1 Configuration cycles. This allows the configuration registers of a particular function in a multi-function device to be accessed. The GMCHM ignores configuration cycles to Devices 1 if the function number is not equal to 0. Register Number. This field selects one register within a particular Bus, Device, and Function as specified by the other fields in the Configuration Address Register. This field is mapped to GAD[7:2] during AGP/PCI1 Configuration cycles. Reserved.
15:11
10:8
7:2
1:0
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4.4.2
CONFIG_DATA - Configuration Data Register
I/O Address: Default Value: Access: Size: 0CFCh 00000000h Read/Write 32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS.
31
0
0
Bit Default
Configuration Data Window
Bit 31:0
Descriptions Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, any I/O access to the CONFIG_DATA register will be mapped to configuration space using the contents of CONFIG_ADDRESS.
4.5
GMCH-M Internal Device Registers
Table 18 below shows the nomenclature of access attributes for the configuration space of each device.
Table 18. Nomenclature for Access Attributes
RO R/W R/WC R/WO L Read Only. If a register is read only, writes to this register have no effect. Read/Write. A register with this attribute can be read and written Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. Read/Write Once. A register bit with this attribute can be written to only once after power up. After the first write, the bit becomes read only. Lock. A register bit with this attribute becomes Read Only after a lock bit is set.
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4.5.1
SDRAM Controller/Host-hub Interface Device Registers Device #0
Table 19 shows the GMCH-M configuration space for device #0. An "s" in the Default Value field means that a strap determines the power-up default value for that bit.
Table 19. Host-Hub I/F Bridge/SDRAM Controller Configuration Space (Device #0)
Address Offset 00-01h 02-03h 04-05h 06-07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10-13h 14-2Bh 2C-2Dh 2E-2Fh 30-33h 34h 35-3Fh 40-44h 45-47h 48-4Bh 4C-4Fh 50-51h 52-53h 54-55h 56-57h 58h 59-5Fh Register Symbol VID DID PCICMD PCISTS RID SUBC BCC MLT HDR APBASE SVID SID CAPPTR RRBAR GCC0 GCC1 FDHC PAM[6:0] Register Name Vendor Identification Device Identification PCI Command Register PCI Status Register Revision Identification Intel Reserved Sub-Class Code Base Class Code Intel Reserved Master Latency Timer Header Type Intel Reserved Aperture Base Configuration Intel Reserved Subsystem Vendor Identification Subsystem Identification Intel Reserved Capabilities Pointer Intel Reserved Intel Reserved Intel Reserved Register Range Base Address Intel Reserved GMCH Control Register 0 GMCH Control Register 1 Intel Reserved Intel Reserved Fixed DRAM Hole Control Programmable Attribute Map (7 registers) Default Value 8086h 3575h 0006h 0010h 00h 00h 06h 00h 00h 00000008h 00h 00h 40h 00000000h A072h 0000h 00h 00h Access RO RO R/W RO, R/WC RO RO RO RO RO R/W, RO R/WO R/WO RO R/W, RO R/W, RO R/W R/W R/W
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60-67h 68-6Fh 70-71h 72-77h 78-7Bh 7C-7Fh 80-8Bh 8C-8Fh 90h 91h 92-93h 94-95h 96h 97h 98-9F A0-A3h A4-A7h A8-ABh AC-AFh B0-B1h B2-B3h B4h B5-B7h B8-BBh BCh BDh BE-BFh C2-EBh EC-EFh F0-FFh
DRB[7:0] DRA[1:0] DRT DRC DTC SMRAM ESMRAMC ERRSTS ERRCMD ACAPID AGPSTAT AGPCMD AGPCTRL AFT APSIZE ATTBASE AMTT LPTT BUFF_SC -
DRAM Row Boundary Register Intel Reserved DRAM Row Attributes Intel Reserved DRAM Timing Register DRAM Control Intel Reserved DRAM Throttling Control Register System Management RAM Control Reg. Extended System Management RAM Control Register Error Status Register Error Command Register Intel Reserved Intel Reserved Intel Reserved AGP Capability Identifier AGP Status Register AGP Command Register Intel Reserved AGP Control Register AGP Functional Test Register AGP Aperture Size Intel Reserved Aperture Translation Table AGP Interface Multi-Transaction Timer Register Low Priority Transaction Timer Register Intel Reserved Intel Reserved System Memory Buffer Strength Control Register Intel Reserved
00h FFh 00000010h 00000000h 00000000h 02h 38h 0000h 0000h 00200002h 1F000217h 00000000h 00h 0000h 0000h 00h 00000000h 00h 00h 00000000h -
R/W/L R/W/L R/W R/W R/W/L R/W/L R/W R/W R/W RO RO RW R/W R/W R/W R/W R/W R/W R/W -
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4.5.1.1
VID - Vendor Identification Register - Device #0
Address Offset: Default Value: Attribute: Size: 00 - 01h 8086h Read Only 16 bits
The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. Default Value=1000/0000/1000/0110.
4.5.1.2
DID - Device Identification Register - Device #0
Address Offset: Default Value: Attribute: Size: 02 - 03h 3575h Read Only 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Device Identification Number. This is a 16-bit value assigned to the GMCH-M Host-hub interface Bridge, Device #0. Default Value=0011/0101/0111/0101.
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4.5.1.3
PCICMD - PCI Command Register - Device #0
Address Offset: Default Value: Access: Size 04-05h 0006h Read/Write 16 bits
Since GMCH-M Device #0 is the host-to-Hub Interface bridge, many of the PCI specific bits in this register don't apply.
Bit 15:10 9 Description Reserved. Fast Back-to-Back. This bit controls whether or not the master can do fast back-to-back write. Since device #0 is strictly a target this bit is not implemented and is hardwired to 0. Writes to this bit position have no affect. Default Value=0. 8 SERR Enable (SERRE). This bit is a global enable bit for Device #0 SERR messaging. The GMCH-M does not have an SERR# signal. The GMCH-M communicates the SERR# condition by sending an SERR message to the ICH. If this bit is set to a 1, the GMCH-M is enabled to generate SERR messages over Hub Interface for specific Device #0 error conditions that are individually enabled in the ERRCMD register. The error status is reported in the ERRSTS and PCISTS registers. If SERRE is reset to 0, then the SERR message is not generated by the GMCH-M for Device #0.NOTE: This bit only controls SERR messaging for the Device #0. Device #1 has its own SERRE bit to control error reporting for error conditions occurring on Device #1. The two control bits are used in a logical OR manner to enable the SERR Hub Interface message mechanism. Default Value=0. 7 Address/Data Stepping. Address/data stepping is not implemented in the GMCH-M, and this bit is hardwired to 0. Writes to this bit position have no effect. Default Value=0. 6 Parity Error Enable (PERRE). PERR# is not implemented by the GMCH-M, and this bit is hardwired to 0. Writes to this bit position have no effect. Default Value=0. 5 VGA Palette Snoop. The GMCH-M does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Default Value=0. 4 Memory Write and Invalidate Enable. The GMCH-M will never use this command and this bit is hardwired to 0. Writes to this bit position have no effect. Default Value=0. 3 Special Cycle Enable. The GMCH-M does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. Default Value=0. 2 Bus Master Enable (BME). The GMCH-M is always enabled as a master on Hub Interface. This bit is hardwired to a 1. Writes to this bit position have no effect. Default Value=1. 1 Memory Access Enable (MAE). The GMCH-M always allows access to main memory. This bit is not implemented and is hardwired to 1. Writes to this bit position have no effect. Default Value=1. 0 I/O Access Enable (IOAE). This bit is not implemented in the GMCH-M and is hardwired to a 0. Writes to this bit position have no effect. Default Value=0.
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4.5.1.4
PCISTS - PCI Status Register - Device #0
Address Offset: Default Value: Access: Size: 06-07h 0010h Read Only, Read/Write Clear 16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's Hub Interface. Bit 14 is read/write clear. All other bits are Read Only. Since GMCH-M Device #0 is the host-to-Hub Interface bridge, many of the PCI specific bits in this register don't apply.
Bit 15
Description Detected Parity Error (DPE). This bit is hardwired to a 0. Writes to this bit position have no affect. Default Value=0.
14
Signaled System Error (SSE). This bit is set to 1 when GMCH-M Device #0 generates an SERR message over Hub Interface for any enabled Device #0 error condition. Device #0 error conditions are enabled in the PCICMD and ERRCMD registers. Device #0 error flags are read/reset from the PCISTS or ERRSTS registers. Software sets SSE to 0 by writing a 1 to this bit. Default Value=0.
13
Received Master Abort Status (RMAS). This bit is set when the GMCH-M generates a Hub Interface request that receives a Master Abort completion packet. Software clears this bit by writing a 1 to it. Default Value=0.
12
Received Target Abort Status (RTAS). This bit is set when the GMCH-M generates a Hub Interface request that receives a Target Abort completion packet. Software clears this bit by writing a 1 to it. Default Value=0.
11
Signaled Target Abort Status (STAS). The GMCH-M will not generate a Target Abort Hub Interface completion packet. This bit is not implemented in the GMCH-M and is hardwired to a 0. Writes to this bit position have no effect. Default Value=0.
10:9
DEVSEL# Timing (DEVT). Hub Interface does not comprehend DEVSEL# protocol. These bits are hardwired to "00". Writes to these bits have no effect. Default Value=00.
8
Data Parity Detected (DPD). GMCH-M does not support parity on Hub Interface. This bit is hardwired to a 0. Writes to this bit position have no effect. Default Value=0.
7
Fast Back-to-Back (FB2B). Hub Interface does not comprehend PCI Fast Back-to-Back protocol. This bit is hardwired to 0. Writes to this bit position have no effect. Default Value=0.
6:5 4
Reserved. Capability List (CLIST). This bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. A list of new capabilities is accessed via register CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the Capabilities linked list begins. Default Value=1.
3:0
Reserved.
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RID - Revision Identification Register - Device #0
Address Offset: Default Value: Access: Size: 08h 00h Read Only 8 bits
This register contains the revision number of the GMCH-M Device #0. These bits are read only and writes to this register have no effect.
Bit 7:0
Description Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the GMCH-M Device #0. For the A-0 Stepping, RID is 00h. Default Value=0000/0000.
4.5.1.6
SUBC - Sub-Class Code Register - Device #0
Address Offset: Default Value: Access: Size: 0Ah 00h Read Only 8 bits
This register contains the Sub-Class Code for the GMCH-M Device #0. This code is 00h indicating a Host Bridge device. The register is read only.
Bit 7:0
Description Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into which the GMCHM falls. The code is 00h indicating a Host Bridge. Default Value=0000/0000.
4.5.1.7
BCC - Base Class Code Register - Device #0
Address Offset: Default Value: Access: Size: 0Bh 06h Read Only 8 bits
This register contains the Base Class Code of the GMCH-M Device #0. This code is 06h indicating a Bridge device. This register is read only.
Bit 7:0
Description Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the GMCH-M. This code has the value 06h. Default Value=0000/0110.
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4.5.1.8
MLT - Master Latency Timer Register - Device #0
Address Offset: Default Value: Access: Size: 0Dh 00h Read Only 8 bits
Hub Interface does not comprehend the concept of a Master Latency Timer. Therefore the functionality of this register is not implemented and the register is hardwired to 0.
Bit 7:0
Description These bits are hardwired to 0. Writes have no affect. Default Value=0000/0000.
4.5.1.9
HDR - Header Type Register - Device #0
Address Offset: Default Value: Access: Size: 0Eh 00h Read Only 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0
Descriptions This read only field always returns 0 when read and writes have no affect. Default Value=0000/0000.
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4.5.1.10
APBASE - Aperture Base Configuration Register - Device #0
Address Offset: Default Value: Access: Size: 10-13h 00000008h Read/Write, Read Only 32 bits
The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture. The standard PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to "0" or behave as hardwired to "0"). To allow for flexibility (of the aperture) an additional register called APSIZE is used as a "back-end" register to control which bits of the APBASE will behave as hardwired to "0". This register will be programmed by the GMCH-M specific BIOS code that will run before any of the generic configuration software is run. Note that bit 9 of the GCC0 register at 51-50h is used to prevent accesses to the aperture range before the configuration software initializes this register and the appropriate translation table structure has been established in the main memory.
Bit 31:28
Description Upper Programmable Base Address bits (R/W). These bits are used to locate the range size selected via lower bits 27:4. Default Value = 0000.
27:25
Lower "Hardwired"/Programmable Base Address bits . These bits behave as a "hardwired" or as a programmable depending on the contents of the APSIZE register as defined below: 27 r/w r/w r/w 0 26 r/w r/w 0 0 25 r/w r/w 0 0 Aperture Sizer/w 32 MB 64 MB 128 MB 256 MB
The Default for APSIZE[5:3,0]=0000 with forces default APBASE[27:25] =000 (i.e. all bits respond as "hardwired" to 0). This provides a default to the maximum aperture size of 256MB. The GMCH-M specific BIOS is responsible for selecting smaller size (if required) before PCI configuration software runs and establishes the system address map. Default Value=000. 24:4 3 Hardwired to "0". This forces minimum aperture size selected by this register to be 32 MB. Prefetchable (RO). This bit is hardwired to "1" to identify the Graphics Aperture range as a prefetchable, i.e. there are no side effects on reads, the device returns all bytes on reads regardless of the byte enables, and the GMCH-M may merge processor writes into this range without causing errors. Type (RO). These bits determine addressing type and they are hardwired to "00" to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space. Default Value=00. 0 Memory Space Indicator (RO). Hardwired to "0" to identify aperture range as a memory range.
2:1
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4.5.1.11
SVID - Subsystem Vendor ID - Device #0
Address Offset: Default Value: Access: Size: 2C-2Dh 0000h Read/Write Once 16 bits
This value is used to identify the vendor of the subsystem.
Bit 15:0
Description Subsystem Vendor ID (R/WO). The default value is 00h. This field should be programmed during boot-up. After this field is written once, it becomes read only. Default Value=0000/0000/0000/0000.
4.5.1.12
SID - Subsystem ID - Device #0
Address Offset: Default Value: Access: Size: 2E-2Fh 0000h Read/Write Once 16 bits
This value is used to identify a particular subsystem.
Bit 15:0
Description Subsystem ID (R/WO). The default value is 00h. This field should be programmed during boot-up. After this field is written once, it becomes read only. Default Value=0000/0000/0000/0000.
4.5.1.13
CAPPTR - Capabilities Pointer - Device #0
Address Offset: Default Value: Access: Size: 34h 40h Read Only 8 bits
The CAPPTR provides the offset that is the pointer to the location where the first capability register set is located.
Bit 7:0
Description Pointer to the start of Capabilities Register Block. The value in this field is 40h. Default Value=0100/0000.
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4.5.1.14
RRBAR - Register Range Base Address Register - Device #0
Address Offset: Default Value: Access: Size: 48-4Bh 00000000h Read/Write, Read Only 32 bits
This register requests a 256-KB allocation for the Device registers. The base address is defined by bits 31 to 18 and can be used to access device configuration registers. Only Dword aligned writes are allowed to this space. See Table below for address map within the 512-KB space. This addressing mechanism may be used to write to registers that modify the device address map (includes all the BARs, PAMs, SMM registers, Pre-Allocated Memory registers etc). However, before using or allowing the use of the modified address map the BIOS must synchronize using an IO or Read cycle. Note that bit 8 of the GCC0 register at 51-50h is used to prevent accesses to this range before the configuration software initializes this register.
Bit 31:18
Description Memory Base Address-R/W. Set by the OS, these bits correspond to address signals [31:18]. Default Value=0000/0000/0000/0.
17:15
Address Mask-RO. Hardwired to 0s to indicate 512-KB address range. The Minimum size that can be requested by converting all these bits to R/W would be 64 KB. Default Value=000.
15:8 7:0
Reserved. Hardwired to 00h. Scratch Pad Size-RO, Hardwired to "00h". 00h = 256B FFh = 64 KB Default Value=0000/0000.
Address Range Description Sub Ranges 00000h to 0003Fh 00000h to 3FFFFhDevice 0 Space 00040h to 000FFh 00100h to 3FEFFh 3FF00h to 3FFFFh Read Only: Maps to 00-3Fh of Device #0 P&P register space. Read/Write: Maps to 40-FFh of Device #0 P&P register space. Read/Write: Extended Register Space. Reserved. Scratch Pad Registers: 256 B, D-word read/write-able.
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4.5.1.15
GCC0 - GMCH Control Register #0 - Device #0
Address Offset: Default Value: Access: Size: 50-51h A072h Read/Write, Read Only 16 bits
Bit 15 14:12
Descriptions Reserved Low Priority Grace Period. This value is loaded in SDRAM Arbiter when a request is ongoing and a higher priority request is presented to the Arbiter. The arbiter continues to grant the first request for this specified number of page hits (1KB). If the first requester causes a page miss or stops requesting the arbiter will switch to the higher priority requester. (A request equals a Oct-word a.k.a dual-oct byte) 000 = 00 001 = 04 010 = 08 (Default) 011 = 16 100 = 24 101 = 32 110 = Reserved 111 = Reserved Default Value=010. Recommended Value without Internal Graphics = 011 16
11
Scratch Pad Enable. This bit when set to a "1", allows the upper 256 Bytes of Device #0 RRBAR space to be mapped to Scratch Pad Ram in the device. Once D_LCK is set, this bit becomes read only. Note: The BIOS can use the scratch pad area when devices on the AGP bus are inactive (Not capable of using the AGP Pipe or Side-Band command bus to issue read cycles to Main Memory). Default Value=0.
10 9
Reserved. Aperture Access Global Enable (R/W). This bit is used to prevent access to the aperture from any port (CPU, PCI0 or AGP/PCI1) before the aperture range is established by the configuration software and appropriate translation table in the main SDRAM has been initialized. It must be set after system is fully configured for aperture accesses. Default Value=0.
8
RRBAR Access Enable. This bit when set to a "1", enables the RRBAR space. When "0", accesses will not decode to register range. Default Value=0.
7 6:4
Reserved IOQ request Grant Ceiling. This value is loaded in SDRAM Arbiter when an IOQ request is granted. It provides a grant for the duration specified for as long as the request is active or until a fixed higher priority request needs to be serviced. 111 = Infinite Ceiling (Default) 110 = 64 101 = 48 100 = 32 011 = 24 010 = 16 001 = 08
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000 = 04 Default Value=111. Recommended Value = 010 3:1 0 Reserved MDA Present (MDAP) (R/W). This bit works with the VGA Enable bit in the BCTRL register of device 1 to control the routing of CPU initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set when the VGA Enable bit is not set. If the VGA enable bit is set, then accesses to IO address range x3BCh-x3BFh are forwarded to Hub Interface. If the VGA enable bit is not set then accesses to IO address range x3BCh-x3BFh are treated just like any other IO accesses i.e. the cycles are forwarded to AGP if the address is within IOBASE and IOLIMIT and ISA enable bit is not set, otherwise they are forwarded to Hub Interface. MDA resources are defined as the following: Memory: 0B0000h - 0B7FFFhI/O: I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in decode) Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to Hub Interface even if the reference includes I/O locations not listed above. The following table shows the behavior for all combinations of MDA and VGA: VGA Default 0 0 1 1 Default Value=0. MDA 0 1 0 1 Behavior All References to MDA and VGA go to Hub Interface Illegal Combination (DO NOT USE) All References to VGA go to AGP/PCI. MDA-only references (I/O address 3BF and aliases) will go to Hub Interface. VGA References go to AGP/PCI; MDA References go to Hub Interface 16
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4.5.1.16
GCC1--GMCH Control Register #1 - Device #0
Address Offset: Default Value: Access: Size:
Bit 15:7 6:4
52-53h 0000h Read/Write 16 bits
Descriptions Reserved Graphics Mode Select (GMS). Default Value = 000
3
Device #2 Disable When set to "1" this bit disables Device #2 and all associated spaces. Default Value = 0
2
Device #2 Function 1 Enable When set to "1", enables the second function within Device #2. Default Value = 0
1
IGD VGA Disable (IVD) Default Value = 0
0
Device 2: Graphics Memory Size Default Value = 0
4.5.1.17
FDHC - Fixed DRAM Hole Control Register - Device #0
Address Offset: Default Value: Access: Size: 58h 00h Read/Write 8 bits
This 8-bit register controls a single fixed SDRAM hole: 15-16 MB.
Bit 7
Description Hole Enable (HEN). This field enables a memory hole in SDRAM space. Host cycles matching an enabled hole are passed on to ICH3-M through Hub Interface. Hub Interface cycles matching an enabled hole will be ignored by the GMCH-M. Note that a selected hole is not re-mapped. Bit 7 0 1 Default Value=0. Hole Enabled None 15M-16M (1M bytes)
6:0
Reserved.
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4.5.1.18
PAM(6:0) - Programmable Attribute Map Registers - Device #0
Address Offset: Default Value: Attribute: Size: 59 - 5Fh 00h Read/Write 4 bits/register, 14 registers
The GMCH-M allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 640 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features. Cacheability of these areas is controlled via the MTRR registers in the P6 processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to both host, AGP/PCI and Hub Interface initiator accesses to the PAM areas. These attributes are: RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding memory segment are claimed by the GMCH-M and directed to main memory. Conversely, when RE = 0, the host read accesses are directed to PCI0. WE - Write Enable. When WE = 1, the host write accesses to the corresponding memory segment are claimed by the GMCH-M and directed to main memory. Conversely, when WE = 0, the host write accesses are directed to PCI0. The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit field. The 4 bits that control each region have the same encoding and are defined in the following table.
Table 20. Attribute Bit Assignment
Bits [7, 3] Reserved X Bits [6, 2] Reserved X Bits [5, 1] WE 0 Bits [4, 0] RE 0 Description Disabled. SDRAM is disabled and all accesses are directed to Hub Interface. The GMCH-M does not respond as a AGP/PCI or Hub Interface target for any read or write access to this area. Read Only. Reads are forwarded to SDRAM and writes are forwarded to Hub Interface for termination. This write protects the corresponding memory segment. The GMCH-M will respond as a AGP/PCI or Hub Interface target for read accesses but not for any write accesses. Write Only. Writes are forwarded to SDRAM and reads are forwarded to the Hub Interface for termination. The GMCH-M will respond as an AGP/PCI or Hub Interface target for write accesses but not for any read accesses. Read/Write. This is the normal operating mode of main memory. Both read and write cycles from the host are claimed by the GMCH-M and forwarded to SDRAM. The GMCH-M will respond as a AGP/PCI or Hub Interface target for both read and write accesses.
X
X
0
1
X
X
1
0
X
X
1
1
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As an example, consider a BIOS that is implemented on the expansion bus. During the initialization process, the BIOS can be shadowed in main memory to increase the system performance. When BIOS is shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to write only. The BIOS is shadowed by first doing a read of that address. This read is forwarded to the expansion bus. The host then does a write of the same address, which is directed to main memory. After the BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. Figure 8 and Table 21 show the PAM registers and the associated attribute bits:
Figure 8. PAM Registers
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Table 21. PAM Registers and Associated Memory Segments
PAM Reg PAM0[3:0] PAM0[7:4] PAM1[3:0] PAM1[7:4] PAM2[3:0] PAM2[7:4] PAM3[3:0] PAM3[7:4] PAM4[3:0] PAM4[7:4] PAM5[3:0] PAM5[7:4] PAM6[3:0] PAM6[7:4] Attribute Bits Reserved R R WE RE R R WE RE R R WE RE R R WE RE R R WE RE R R WE RE R R WE RE R R WE RE R R WE RE R R WE RE R R WE RE R R WE RE R R WE RE 0F0000h - 0FFFFFh 0C0000h - 0C3FFFh 0C4000h - 0C7FFFh 0C8000h - 0CBFFFh 0CC000h- 0CFFFFh 0D0000h- 0D3FFFh 0D4000h- 0D7FFFh 0D8000h- 0DBFFFh 0DC000h- 0DFFFFh 0E0000h- 0E3FFFh 0E4000h- 0E7FFFh 0E8000h- 0EBFFFh 0EC000h- 0EFFFFh BIOS Area ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension Memory Segment Comments Offset 59h 59h 5Ah 5Ah 5Bh 5Bh 5Ch 5Ch 5Dh 5Dh 5Eh 5Eh 5Fh 5Fh
For details on overall system address mapping scheme see the Address Decoding Section of this document. DOS Application Area (00000h-9FFFh) The DOS area is 640 KB in size and it is further divided into two parts. The 512-KB area at 0 to 7FFFFh is always mapped to the main memory controlled by the GMCH-M, while the 128-KB address range from 080000 to 09FFFFh can be mapped to PCI0 or to main SDRAM. By default this range is mapped to main memory and can be declared as a main memory hole (accesses forwarded to PCI0) via GMCHM's FDHC configuration register. Video Buffer Area (A0000h-BFFFFh) This 128-KB area is not controlled by attribute bits. The host -initiated cycles in this region are always forwarded to either PCI0 or AGP/PCI1 or PCI2 unless this range is accessed in SMM mode. Routing of accesses is controlled by the Legacy VGA control mechanism of the "virtual" PCI-PCI bridge device embedded within the GMCH-M. This area can be programmed as SMM area via the SMRAM register. When used as an SMM space this range cannot be accessed from Hub Interface or AGP. Expansion Area (C0000h-DFFFFh) This 128-KB area is divided into eight 16-KB segments that can be assigned with different attributes via PAM control register as defined by Table 21. Extended System BIOS Area (E0000h-EFFFFh) This 64-KB area is divided into four 16-KB segments that can be assigned with different attributes via PAM control register as defined by the Table 21.
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System BIOS Area (F0000h-FFFFFh) This area is a single 64-KB segment that can be assigned with different attributes via PAM control register as defined by the Table 21.
4.5.1.19
DRB -- DRAM Row Boundary Register - Device #0
Address Offset: Default Value: Access: Size: 60-67h 00h Read/Write (Read_Only if D_LCK = 1) 8 bits
Row Boundary Register defines the upper boundary address of each SDRAM row in 32-MB granularity. Each row has its own DRB register. Contents of these 8-bit registers represent the boundary address in 32-MB granularity. For example, a value of 1 indicates 32 MB.
Row0: Row1: Row2: Row3: Row4: Row5: Row6: Row7: 60h 61h 62h 63h 64h: Reserved 65h: Reserved 66h: Reserved 67h: Reserved
DRB0 = Total memory in row0 (in 32 Mbytes) DRB1 = Total memory in row0 + row1 (in 32 Mbytes) ---DRB4 = Total memory in row0 + row1 + row2 + row3 + (in 32 Mbytes) Note: The number of DRB registers and number of bits per DRB register are system dependent. For example, a system that support 4 rows of SDRAM and a max memory of 1.0 GB needs only 4 DRB registers and 4 bits per DRB. GMCH-M supports 4 physical rows of Single data rate SDRAM in 2 SO-DIMMs. The width of a row is 64 bits. Each SO-DIMM/Row is represented by a byte. Each byte has the following format. GMCH-M supported maximum memory size: 1.0 GB.
Bit 7:0
Description SDRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses for each SDRAM row. Bits 6:0 of this field are compared against the address lines A[31:25] to determine the upper address limit of a particular row. Bit 7 must be Zero. Default Value=0000/0000.
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4.5.1.20
DRA -- DRAM Row Attribute Register - Device #0
Address Offset: Default Value: Access: Size: Row0, 1: Row2, 3: 70-71h FFh Read/Write (Read_Only if D_LCK = 1) 8 bits 70h 71h
Row Attribute Register defines the page size of each row.
7 R 7 R 6 Row attribute for Row3 6 Row attribute for Row1 4 4 3 R 3 R 2 Row Attribute for Row0 2 Row Attribute for Row2 0 0
Bit 3:0(7:4)
Description Row Attribute: This 4-bit filed defines the page size of the row. Page Size is dependent on the technology as shown in the table below. Bits 3:0 "0000" "0001" "0010" "0011" "1111" Page Size 2KB 4 KB 8 KB 16 KB. Empty Row.
All Other Combinations are Reserved. Default Value=1111.
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4.5.1.21
DRT--DRAM Timing Register - Device #0
Address Offset: Default Value: Access: Size: 78-7Bh 00000010h Read/Write 32 bits
This register controls the timing of the SDRAM Controller.
Bit 31:19 18:16
Description Reserved. DRAM Idle Timer: This field determines the number of clocks the SDRAM controller allows a row in the idle state (un-accessed) before pre-charging all pages in that row; or powering down that row based on the settings of bit 28 and bit 14 of DRC. Bit[18:16] 000 001 010 011 100 101 110 111 DRC 28 0 0 1 1 Idle clocks before Action Infinite (Counter is disabled and no action is taken) 0 (Not Supported on GMCH-M as this setting requires auto precharge) 8 16 64 256 512 1024 DRC 14 0 1 0 1 Action on Counter Expiration. None (Counter Disabled) Pre-Charge All Power Down and De-assert CKE, Pages open. Pre-charge All, Power Down and De-assert CKE
(Pwr Dwn Enbl) (Page Cls Enbl)
Default Value=000. Recommended settings for DRC 28=1, DRC 14=1 and DRT 18:16 =010. 15:11 10 Reserved Activate to Precharge delay (tRAS). This bit controls the number of CLKs for tRAS. 0 = tRAS = 7 CLKs 1 = tRAS = 5 CLKs. Default Value=0. 9:6 5:4 Reserved CAS# Latency (tCL). This bit controls the number of CLKs between when a read command is sampled by the SDRAM and when GMCH-M samples read data from the SDRAM. 00 = Reserved 01 = 3 10 = 2 11 = Reserved Default Value=01. 3 Reserved
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Bit 2
Description DRAM RAS# to CAS# Delay (tRCD). This bit controls the number of CLKs from a Row Activate command to a read or write command. 0 = 3 clocks will be inserted between a row activate command and either a read or write command. 1 = 2 clocks will be inserted between a row activate command and either a read or write command. Default Value=0.
1 0
Reserved DRAM RAS# Precharge (tRP). This bit controls the number of CLKs for RAS# pre-charge. 0 = 3 clocks of RAS# pre-charge are provided. 1 = 2 clocks of RAS# pre-charge are provided Default Value=0.
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4.5.1.22
DRC - DRAM Controller Mode Register - Device #0
Address Offset: Default Value: Access: Size:
Bit 31:30 29
7C-7Fh 00000000h Read/Write 32 bits
Description Specification Revision Number. Hardwired to "00" on GMCH-M. Initialization Complete (IC): Setting this bit to a "1" enables SDRAM refreshes. On power up and S3 exit, the BIOS initializes the SDRAM array and sets this bit to a "1". This bit works in combination with the RMS bits in controlling refresh state: IC RMS Refresh State 0 XXX X 000 1 001 1 010 1 011 1 111 OFF OFF ON ON ON ON
Default Value=0. 28 DRAM Row Power- Mgmt Enable: When this bit is set to a 1, a SDRAM row is powered down (issued a power down command and CKE de-asserted) after the SDRAM idle timer (as programmed in DRT) expires. During a refresh, rows in the low power state are powered up and refreshed. Hence, coming out of a refresh all rows will be powered up. Default Value=0. 27 26:24 Reserved. Active Row Count: This field determines the number of rows the SDRAM controller allows in the active state if SDRAM row power management is enabled (bit 28). All populated rows not in the active state are in power down. An access to a row in power down will cause that row to exit power down, following that the LRU row is placed into power down if the number of active rows is greater than that allowed by this register. Bit[26:24] 000 001 010 011 100 101 110 111 Maximum number of Active Rows All rows allowed to be in active state. 1 Row 2 Rows 3 Rows 4 Rows Reserved Reserved Reserved
Default Value=000. 23:20 19:15 14 Reserved. Reserved. Page Close Enable: When this bit is set to a 1, SDRAM row pages are closed after the SDRAM idle timer (as programmed in DRT) expires. Default Value=0. 13:11 Reserved
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Bit 10:8
Description Refresh Mode Select (RMS): Bits Determine if Refresh is enabled and Refresh Rate. 000: Refresh Disabled. 001: Refresh Enabled. Refresh interval 15.6 s. 010: Refresh Enabled. Refresh interval 7.8 s. 011: Reserved 111: Refresh Enabled. Refresh interval 128 Clocks. (Fast Refresh Mode)
All Other Combinations are reserved.
Default Value=000. 7 6:4 Reserved Mode Select (SMS). These bits select the special operational mode of the GMCH-M SDRAM interface. The special modes are intended for initialization at power up. 000 = Self refresh (Default). In this mode CKEs are de-asserted. All other values cause CKE assertion. The exception is in C3/S1/S3 this register is programmed to "normal operation", the DRAMs are in self-refresh, and CKEs are de-asserted. 001 = NOP Command Enable. In this mode all CPU cycles to SDRAM result in a NOP Command on the SDRAM interface. 010 = All Banks Pre-charge Enable. In this mode all CPU cycles to SDRAM result in an All Banks Pre-charge Command on the SDRAM interface. 011 = Mode Register Set Enable. In this mode all CPU cycles to SDRAM result in a mode register set command on the SDRAM interface. The Command is driven on the MA[12:0] lines. MA[2:0] must always be driven to 010 for burst of 4 mode. MA3 must be driven to 1 for interleave wrap type. MA[6:4] needs to be driven based on the value programmed in the CAS# Latency field. CAS Latency 2 Clocks 3 Clocks MA[6:4] 010 011
MA[12:7] must be driven to 00000. BIOS must calculate and drive the correct host address for each row of memory such that the command is driven on the MA[12:0] lines. 100 = Reserved. 101 = Reserved. 110 = CBR Refresh Enable. In this mode all CPU cycles to SDRAM result in a CBR cycle on the SDRAM interface. 111 = Normal Operation. Default Value=000. 3:2 1:0 Reserved. Reserved. correct
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4.5.1.23
DTC - DRAM Throttling Control Register - Device #0.
Offset Address: Default Value: Access: Size: 8C-8Fh 0000_0000h Read/Write/Lock 32 bits
Throttling is independent for Reads and Writes. If the number of Oct-Words (16 bytes) read/written during a global dram sampling window (GDSW) exceeds the DRAM Bandwidth Threshold defined below, then the DRAM throttling mechanism will be invoked to limit DRAM reads/writes to a lower bandwidth checked and throttled over smaller time windows. After exceeding the limit, throttling will be active for the remainder of the current GDSW and for the next GDSW after which it will return to non-throttling mode. The throttling mechanism accounts for the actual bandwidth consumed during the sampling window, by reducing the allowed bandwidth within the smaller throttling window based on the bandwidth consumed during the sampling period.
Bandwidth Limit 74%
Range within GDSW (as a %age of GDSW) where Bandwidth Exceeded the Limit 88 - 100% 74 - 88%
Bandwidth Allowed for rest of current, next GDSW (% of Adaptive throttle Window) 68% 60% 54% 48% 44% 38% 34% 30% 32% 28% 26% 24%
60%
88 - 100% 74 - 88% 60 - 74%
46%
82 - 100% 64 - 82% 46 - 64%
36%
84 - 100% 66 - 84% 50 - 66% 36 - 50%
Bits 31
Description Throttle Lock (TLOCK): This bit secures the SDRAM throttling control register. Once a `1' is written to this bit, all of the configuration register bits in DTC (including TLOCK) documented below become readonly. Default Value=0.
30 29:28
Intel Reserved DRAM Throttle Mode (TMODE): Bits 00 01 10 Mode Throttling turned off. Bandwidth Counter mechanism is enabled. When bandwidth exceeds threshold set in the r/w PTC field, DRAM read/write throttling begins. Thermal Sensor based throttling enabled. When the device's thermal sensor is tripped DRAM
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Bits
Description Write throttling begins based on settings programmed in WPTC. Read throttling is disabled. 11 With this setting Thermal Sensor and DRAM Counter mechanisms are both enabled. However, read throttling is bandwidth counter triggered only while write throttling is thermal sensor or counter triggered. Both read and write throttling mechanisms use programmed values in the throttle control registers.
Default Value=00 27 26:24 Reserved Read Power Throttle Control. These bits select the Power Throttle Bandwidth Limits for Read operations to System Memory. R/W, RO if Throttle Lock. 000 = No Limit (1067 MB/ 1600 MB/ 2133 MB/Sec) 001 = Limit at 74 % ( 789 MB/ 1184 MB/ 1578 MB/Sec) 010 = Limit at 60 % ( 640 MB/ 0960 MB/ 1280 MB /Sec) 011 = Limit at 46% 100 = Limit at 36% 101 = Reserved. 110 = Reserved. 111 = Reserved. Default Value=000 23 22:20 Reserved Write Power Throttle Control. These bits select the Power Throttle Bandwidth Limits for Write operations to System Memory. R/W, RO if Throttle Lock. 000 = No Limit (1067 MB/ 1600 MB/ 2133 MB/Sec) 001 = Limit at 74 % ( 789 MB/ 1184 MB/ 1578 MB/Sec) 010 = Limit at 60 % ( 640 MB/ 0960 MB/ 1280 MB /Sec) 011 = Limit at 46% 100 = Limit at 36% 101 = Reserved. 110 = Reserved. 111 = Reserved. Default Value=000 19:16 15:8 Reserved Global DRAM Sampling Window (GDSW): This eight bit value is multiplied by 4 to define the length of time in milliseconds (0-1020) over which the number of OctWords (16 bytes) read/written is counted and Throttling is imposed. Default Value=00000000. 7:0 Reserved ( 491 MB/ 0736 MB/ 0981 MB Sec) ( 384 MB/ 0576 MB/ 0768 MB Sec) ( 491 MB/ 0736 MB/ 0981 MB Sec) ( 384 MB/ 0576 MB/ 0768 MB Sec)
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4.5.1.24
SMRAM - System Management RAM Control Register - Device #0
Address Offset: Default Value: Access: Size: 90h 02h Read/Write/Lock, Read Only 8 bits
The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
Bit 7 6
Description Reserved SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space SDRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When D_LCK is set to a 1, D_OPEN is reset to 0 and becomes read only. Default Value=0.
5
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not accessible to data references, even if SMM decode is active. Code references may still access SMM space SDRAM. This will allow SMM software to reference "through" SMM space to update the display even when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Default Value=0.
4
SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK, D_OPEN, G_SMRAME, C_BASE_SEG, GMS, DRB, DRA, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read only. GBA[15:0] and GAR[15:0] associated with the SDRAM controller also become read only after D_LCK is set. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function. Default Value=0.
3
Global SMRAM Enable (G_SMRAME). If set to a 1, then Compatible SMRAM functions is enabled, providing 128 KB of SDRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function this bit has be set to 1. Refer to the section on SMM for more details. Once D_LCK is set, this bit becomes read only. Default Value=0.
2:0
Compatible SMM Space Base Segment (C_BASE_SEG) (RO). This field indicates the location of SMM space. "SMM DRAM" is not remapped. It is simply "made visible" if the conditions are right to access SMM space, otherwise the access is forwarded to Hub Interface. C_BASE_SEG is hardwired to 010 to indicate that the GMCH-M supports the SMM space at A0000hBFFFFh. Default Value=010.
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4.5.1.25
ESMRAMC - Extended System Management RAM Control Register Device #0
Address Offset: Default Value: Access: Size: 91h 38h Read/Write 8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MB.
Bit 7
Description H_SMRAM_EN (H_SMRAME): Controls the SMM memory space location (i.e. above 1 MB or below 1MB) When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM memory space is enabled. SMRAM accesses from 0FEDA0000h to 0FEDBFFFFh are remapped to SDRAM address 000A0000h to 000BFFFFh. Once D_LCK is set, this bit becomes read only. Default Value=0.
6
E_SMRAM_ERR (E_SMERR): This bit is set when CPU accesses the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. It is software's responsibility to clear this bit. The software must write a 1 to this bit to clear it Default Value=0.
5
SMRAM_Cache (SM_CACHE): This bit is forced to `1' by the GMCH-M . Default Value=1.
4
SMRAM_L1_EN (SM_L1): This bit is forced to `1' by the GMCH-M. Default Value=1.
3
SMRAM_L2_EN (SM_L2): This bit is forced to `1' by the GMCH-M. Default Value=1.
2 1
Reserved TSEG_SZ(T_SZ): Selects the size of the TSEG memory block if enabled. This memory is taken from the top of SDRAM space (i.e. TOM - TSEG_SZ), which is no longer claimed by the memory controller. This field decodes as follows: TSEG_SZ 0 1 Description (TOM-512K) to TOM (TOM-1M) to TOM
Once D_LCK is set, this bit becomes read only. Default Value=0. 0 TSEG_EN (T_EN): Enabling of SMRAM memory (TSEG, 512 Kbytes or 1 Mbytes of additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Once D_LCK is set, this bit becomes read only. Default Value=0.
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4.5.1.26
ERRSTS - Error Status Register - Device #0
Address Offset: 92-93h Default Value: 0000h Access: Read/Write Clear Size: 16 bits
This register is used to report various error conditions via Hub interface special cycles. An SERR, SMI, or SCI Error Hub interface special cycle may be generated on a zero to one transition of any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers respectively.
Bit 15:13 12 11 10 9
Description Reserved Reserved Reserved Reserved LOCK to non-DRAM Memory Flag (LCKF). (R/WC) When this bit is set it indicates that a CPU initiated LOCK cycle targeting non-DRAM memory space occurred. Software must write a "1" to clear this status bit Received Refresh Timeout. This Bit is set when 1024 memory core refresh are Queued up. Software must write a "1" to clear this status bit.
8
7 6 5
DRAM Throttle Flag (DTF) (R/WC). When this bit is set it indicates that the DRAM Throttling condition occurred. Software must write a "1" to clear this status bit. Reserved Received Unimplemented Special Cycle Hub interface Completion Packet FLAG (UNSC) (R/WC). When this bit is set it indicates that the GMCH initiated a Hub interface request that was terminated with a Unimplemented Special Cycle completion packet. Software must write a "1" to clear this status bit. AGP Access Outside of Graphics Aperture Flag (OOGF). (R/WC) When this bit is set it indicates that an AGP access occurred to an address that is outside of the graphics aperture range. Software must write a "1" to clear this status bit. Invalid AGP Access Flag (IAAF). (R/WC) When this bit is set to "1" it indicates that an AGP access was attempted outside of the graphics aperture and either to the 640k - 1M range or above the top of memory. Software must write a "1" to clear this status bit. Invalid Graphics Aperture Translation Table Entry Flag (ITTEF). (R/WC) When this bit is set to "1", it indicates that an invalid translation table entry was returned in response to an AGP access to the graphics aperture. Software must write a "1" to clear this status bit. Invalid translation table entries include the following: Invalid bit set in table entry. Translated address hits PAM region. Translated address hits enabled physical SMM space.
4
3
2
1 0
Reserved Reserved
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4.5.1.27
ERRCMD - Error Command Register - Device #0
Address Offset: Default Value: Access: Size: 94-95h 0000h Read/Write 16 bits
This register enables various errors to generate an SERR Hub Interface special cycle. . Since the GMCHM does not have an SERR# signal, SERR messages are passed from the GMCH-M to the ICH3-M over the Hub Interface. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register. Note: An error can generate one and only one Hub Interface error special cycle. The software is responsible to ensure that when an SERR error message is enabled for an error condition, SMI and SCI error messages are disabled for that same error condition.
Bit 15:10 9 Description Reserved. SERR on LOCK to non-SDRAM Memory. When this bit is set to "1", the GMCH-M generates an SERR Hub Interface special cycle when a CPU initiated LOCK transaction targeting non-SDRAM memory space occurs. If this bit is "0" then reporting of this condition is disabled. Default Value=0. 8 SERR on SDRAM Refresh timeout. When this bit is set to "1", the GMCH-M generates an SERR Hub Interface special cycle when a SDRAM Refresh timeout occurs. If this bit is "0" then reporting of this condition is disabled. Default Value=0. 7 SERR on SDRAM Throttle Condition. When this bit is set to "1", the GMCH-M generates an SERR Hub Interface special cycle when a SDRAM Read or Write Throttle condition occurs. If this bit is "0" then reporting of this condition is disabled. Default Value=0. 6 SERR on Receiving Target Abort on Hub Interface. When this bit is set to "1", the GMCH-M generates an SERR Hub Interface special cycle when a GMCH-M originated Hub Interface cycle is terminated with a Target Abort. If this bit is "0" then reporting of this condition is disabled. Default Value=0. 5 SERR on Receiving Unimplemented Special Cycle Hub Interface Completion Packet. When this bit is set to "1", the GMCH-M generates an SERR Hub Interface special cycle when a GMCH-M initiated Hub Interface request is terminated with a Unimplemented Special Cycle completion packet. If this bit is "0" then reporting of this condition is disabled. Default Value=0. 4 SERR on AGP Access Outside of Graphics Aperture. When this bit is set to "1", the GMCH-M generates an SERR Hub Interface special cycle when an AGP access occurs to an address outside of the graphics aperture. If this bit is "0" then reporting of this condition is disabled. Default Value=0. 3 SERR on Invalid AGP Access. When this bit is set to "1", the GMCH-M generates an SERR Hub Interface special cycle when an AGP access occurs to an address outside of the graphics aperture and either to the 640K - 1M range or above the top of memory. Default Value=0. 2 SERR on Access to Invalid Graphics Aperture Translation Table Entry. When this bit is set to "1", the GMCH-M generates an SERR Hub Interface special cycle when an invalid translation table entry was returned in response to a AGP access to the graphics aperture. If this bit is "0" then reporting of this condition via SERR messaging is disabled. Default Value=0. Reserved Reserved
1 0
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Table 22. Summary of GMCH-M Error Sources, Enables and Status Flags
Error Event SDRAM Refresh Timeout Hub I/F Message SERR Enable Bits Required to be Set PCICMD bit 8 ERRCMD bit 8 CPU LOCK to non-SDRAM memory SERR PCICMD bit 8 ERRCMD bit 9 SDRAM Throttle SERR PCICMD bit 8 ERRCMD bit 7 Received Hub Interface Target Abort SERR PCICMD bit 8 ERRCMD bit 6 Unimplemented Special Cycle SERR PCICMD bit 8 ERRCMD bit 5 AGP Access Outside of Graphics Aperture SERR PCICMD bit 8 ERRCMD bit 4 Invalid AGP Access SERR PCICMD bit 8 ERRCMD bit 3 Access to Invalid GTLB Entry SERR PCICMD bit 8 ERRCMD bit 2 AGP PCI Parity Error Detected SERR PCICMD1 bit 8 BCTRL bit 0 AGP PCI Received Target Abort SERR PCICMD1 bit 8 ERRCMD1 bit 0 Status Flags Set PCISTS bit 14 ERRSTS bit 8 PCISTS bit 14 ERRSTS bit 9 PCISTS bit 14 ERRSTS bit 7 PCISTS bit 14 PCISTS bit 12 PCISTS bit 14 ERRSTS bit 5 PCISTS bit 14 ERRSTS bit 4 PCISTS bit 14 ERRSTS bit 3 PCISTS bit 14 ERRSTS bit 2 PCISTS1 bit 14 SSTS bit 15 PCISTS1 bit 14 SSTS bit 12
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4.5.1.28
ACAPID - AGP Capability Identifier Register - Device #0
Address Offset: Default Value: Access: Size: A0-A3h 00200002h Read Only 32 bits
This register provides standard identifier for AGP capability.
Bit 31:24 23:20
Description Reserved Major AGP Revision Number: These bits provide a major revision number of AGP specification to which this version of GMCH-M conforms. These bits are set to the value 0010 to indicate AGP Rev. 2.x. Default Value=0010.
19:16
Minor AGP Revision Number: These bits provide a minor revision number of AGP specification to which this version of GMCH-M conforms. This number is hardwired to value of 0000 (i.e. implying Rev x.0). Together with major revision number, this field identifies GMCH-M as an AGP REV 2.0 compliant device. Default Value=0000.
15:8
Next Capability Pointer: AGP capability is the last capability described via the capability pointer mechanism and therefore these bits are hardwired to 00h to indicate the end of the capability linked list. Default Value=0000/0000.
7:0
AGP Capability ID: This field identifies the linked list item as containing AGP registers. This field has the value 02h as assigned by the PCI SIG. Default Value=0000/0010.
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4.5.1.29
AGPSTAT - AGP Status Register - Device #0
Address Offset: Default Value: Access: Size: A4-A7h 1F000217h Read Only 32 bits
This register reports AGP device capability/status.
Bit 31:24
Description Request Queue. This field is hardwired to 1Fh to indicate a maximum of 32 outstanding AGP command requests can be handled by the GMCH-M. Default =1Fh to allow a maximum of 32 outstanding AGP command requests. Default Value=00011111.
23:10 9
Reserved SBA. This bit indicates that the GMCH-M supports side band addressing. It is hardwired to 1.
8:6 5
Reserved 4G. This bit indicates that the GMCH-M does not support addresses greater than 4 GB. It is hardwired to 0.
4
Fast Writes The GMCH-M supports Fast Writes from the CPU to the AGP master. Fast Writes are disabled. Default Value=1.
3 2:0
Reserved RATE. After reset the GMCH-M reports its data transfer rate capability. Bit 0 identifies if AGP device supports 1x data transfer mode Bit 1 identifies if AGP device supports 2x data transfer mode Bit 2 identifies if AGP device supports 4x data transfer mode. 1x, 2x, and 4x data transfer modes are supported by the GMCH-M. Note: The selected data transfer mode applies to both AD bus and SBA bus. Default Value=111.
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4.5.1.30
AGPCMD - AGP Command Register - Device #0
Address Offset: Default Value: Access: Size: A8-ABh 00000000h Read/Write 32 bits
This register provides control of the AGP operational parameters.
Bit 31:10 9
Description Reserved. SBA Enable. When this bit is set to 1, the side band addressing mechanism is enabled. Default Value=0.
8
AGP Enable. When this bit is reset to 0, the GMCH-M will ignore all AGP operations, including the sync cycle. Any AGP operations received while this bit is set to 1 will be serviced even if this bit is reset to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being delivered in 1X mode the command will be issued. When this bit is set to 1 the GMCH-M will respond to AGP operations delivered via PIPE#, or to operations delivered via SBA if the AGP Side Band Enable bit is also set to 1. Default Value=0.
7:6 5 4
Reserved. 4G. The GMCH-M as an AGP target does not support addressing greater than 4 GB. This bit is hardwired to 0. Fast Write Enable When set to "1" GMCH-M AGP master supports Fast Writes. When set to "0" Fast Writes are disabled. Default Value=0.
3 2:0
Reserved. Data Rate: The settings of these bits determine the AGP data transfer rate. One (and only one) bit in this field must be set to indicate the desired data transfer rate. 001 = 1X (Bit 0) 010 = 2X (Bit 1) 100 = 4x (Bit 2) The same bit must be set on both master and target. Configuration software will update this field by setting only one bit that corresponds to the capability of AGP master (after that capability has been verified by accessing the same functional register within the AGP masters configuration space.) Note that the selected data transfer mode applies to both AD bus and SBA bus. Default Value=000.
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4.5.1.31
AGPCTRL - AGP Control Register - Device #0
Address Offset: Default Value: Access: Size: B0-B1h 00000000h Read/Write 32 bits
This register provides for additional control of the AGP interface.
Bit 31:8 7
Description Reserved GTLB Enable (and GTLB Flush Control) (R/W): Note: This bit can be changed dynamically (i.e. while an access to GTLB occurs). Default Value=0.
6:0
Reserved
4.5.1.32
AFT - AGP Functional Test Register - Device #0
Address Offset: B2-B3h Default Value: 0000h Access: Read/Write Size: 16 bits
This register provides for additional control of the AGP interface.
Bit 15:10 9
Description Reserved PCI Read Buffer Disable. (RW) When set to "1" is disabled. In this mode all data pre-fetched and buffered for a PCI-to-DRAM read will be discarded when that read transaction terminates. This bit defaults to "0".
8:4
AGP PCI1 Discard Timer Time-out Count. (RW) These bits control the length of AGP/PCI1 Delayed Transaction discard time-out for the purpose of enhancing the system testability. Default value is 11111b (31d) for a discard count of 1024d ((value+1)*32).
3:0
Reserved
4.5.1.33
APSIZE Aperture Size - Device #0
Address Offset: Default Value: Access: Size: B4h 00h Read/Write 8 bits
This register determines the effective size of the Graphics Aperture. This register can be updated by the GMCH-M-specific BIOS configuration sequence before the PCI standard bus enumeration sequence. If the register is not updated then a default value will select an aperture of maximum size (i.e. 256 MB). The size of the table that will correspond to a 256 MB aperture is not practical for most applications and
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therefore these bits must be programmed to a smaller practical value that will force adequate address range to be requested via APBASE register from the PCI configuration software.
Bit 7:6 5:3
Description Reserved Graphics Aperture Size (APSIZE) (R/W): Each bit in APSIZE[5:3] operates on similarly ordered bits in APBASE[27:25] of the Aperture Base configuration register. When a particular bit of this field is "0" it forces the similarly ordered bit in APBASE[27:25] to behave as "hardwired" to 0. When a particular bit of this field is set to "1" it allows the corresponding bit of the APBASE[27:25] to be read/write accessible. Only the following combinations are allowed when the Aperture is enabled: Bits[5:3] Aperture Size 111 110 100 000 32 MB 64 MB 128 MB 256 MB
Default for APSIZE[5:3]=000b forces default APBASE[27:25] =000b (i.e. all bits respond as "hardwired" to 0). This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:3]=111b enables APBASE[27:25] as read/write programmable. 2:0 Reserved
4.5.1.34
ATTBASE Aperture Translation Table Base Register - Device #0
Address Offset: Default Value: Access: Size: B8-BBh 00000000h Read/Write 32 bits
This register provides the starting address of the Graphics Aperture Translation Table Base located in the main DRAM. This value is used by the GMCH-M's Graphics Aperture address translation logic (including the GTLB logic) to obtain the appropriate address translation entry required during the translation of the aperture address into a corresponding physical DRAM address. The ATTBASE register may be dynamically changed. Note: The address provided via ATTBASE is 4-KB aligned.
Bit 31: 12 11:0 Description This field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in main memory. Reserved
4.5.1.35
AMTTAGP Interface Multi-Transaction Timer Register - Device #0
Address Offset: Default Value: Access: Size: BCh 00h Read/Write 8 bits
AMTT is an 8-bit register that controls the amount of time that the GMCH-M's arbiter allows the AGP/PCI master to perform multiple back-to-back transactions. The GMCH-M's AMTT mechanism is
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used to optimize the performance of the AGP master (using PCI semantics) that performs multiple backto-back transactions to fragmented memory ranges (and as a consequence cannot use long burst transfers). The AMTT mechanism applies to the CPU-AGP/PCI transactions as well and it guarantees to the CPU a fair share of the AGP/PCI interface bandwidth. The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in 66MHz clocks) allotted to the current agent (either AGP PCI master or Host bridge) after which the AGP arbiter may grant the bus to another agent. The default value of AMTT is 00h and disables this function. The AMTT value can be programmed with 8-clock granularity. For example, if the AMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP (66-MHz) clocks.
Bit 7:3
Description Multi-Transaction Timer Count Value. The number programmed in these bits represents the guaranteed time slice (measured in eight 66-MHz clock granularity) allotted to the current agent (either AGP PCI master or Host bridge) after which the AGP arbiter may grant the bus to another agent. Reserved
2:0
4.5.1.36
LPTTLow Priority Transaction Timer Register - Device #0
Address Offset: Default Value: Access: Size: BDh 00h Read/Write 8 bits
LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or Sideband mechanisms. The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in 66MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does not necessarily apply to a single transaction but it can span over multiple low-priority transactions of the same type. After this time expires the AGP arbiter may grant the bus to another agent if there is a pending request. The LPTT does not apply in the case of high-priority request where ownership is transferred directly to the high-priority requesting queue. The default value of LPTT is 00h and disables this function. The LPTT value can be programmed with 8-clock granularity. For example, if the LPTT is programmed to 10h, then the selected value corresponds to the time period of 16 AGP (66-MHz) clocks.
Bit 7:3
Description Low Priority Transaction Timer Count Value. The number of clocks programmed in these bits represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the current low priority AGP transaction data transfer state. Reserved
2:0
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4.5.1.37
BUFF_SC - System Memory Buffer Strength Control Register - Device #0
Address Offset: Default Value: Access: Size EC-EFh 00000000h Read/Write 32 bits
4.5.1.37.1
SDR Drive Strength Register Description
The System Memory Buffer Strength Control Register programs drive strengths and slew rate and for each buffer category based on loading detected by SPD. CS#, CKE, and CLK buffers have independent control for each SO-DIMM and are programmed to the same strength for front and back side of each SO-DIMM. If the BIOS detects different loading on the backside of the SO-DIMM (i.e. 96 MB), it should ignore the devices on the backside of the SO-DIMM.
Bit 31 30
Descriptions Reserved CLK[3:2] Slew Rate. This field sets the slew rate of the CLK[3:2] pins. 0 = Normal slew rate. 1 = Fast slew rate for reduced Tco. Default Value=0.
29
CLK[1:0] Slew Rate. This field sets the slew rate of the CLK[1:0] pins. 0 = Normal slew rate. 1 = Fast slew rate for reduced Tco. Default Value=0.
28 27
Reserved CS[3:2]#, CKE[3:2] Slew Rate. This field sets the slew rate of the CS[3:2]#, CKE[3:2] pins. 0 = Normal slew rate. 1 = Fast slew rate for reduced Tco. Default Value=0.
26
CS[1:0]#, CKE[1:0] Slew Rate. This field sets the slew rate of the CS[1:0]#, CKE[1:0] pins. 0 = Normal slew rate. 1 = Fast slew rate for reduced Tco. Default Value=0.
25
DQ[63:0], DQM[7:0] Slew Rate. This field sets the slew rate of the DQ[63:0], DQM[7:0] pins. 0 = Normal slew rate. 1 = Fast slew rate for reduced Tco. Default Value=0.
24
MA[12:0], BA[1:0], RAS#, CAS#, WE# Slew Rate. This field sets the slew rate of the MA[12:0], BA[1:0], RAS#, CAS#, WE# pins. 0 = Normal slew rate. 1 = Fast slew rate for reduced Tco. Default Value=0.
23:21 20:18
Reserved CLK[3:2] Buffer Strength. This field sets the buffer strength of the CLK[3:2] pins. 000 = 0.75X 001 = 1X
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010 = 1.25X 011 = 1.5X 100 = 2X 101 = 2.5X 110 = 3X 111 = 4X Default Value=000. 17:15 CLK[1:0] Buffer Strength. This field sets the buffer strength of the CLK[1:0] pins. 000 = 0.75X 001 = 1X 010 = 1.25X 011 = 1.5X 100 = 2X 101 = 2.5X 110 = 3X 111 = 4X Default Value=000. 14:12 11:9 RESERVED CS[3:2]#, CKE[3:2] Buffer Strength. This field sets the buffer strength of the CS[3:2]#, CKE[3:2] pins. 000 = 0.75X 001 = 1X 010 = 1.25X 011 = 1.5X 100 = 2X 101 = 2.5X 110 = 3X 111 = invalid Default Value=000. 8:6 CS[1:0]#, CKE[1:0] Buffer Strength. This field sets the buffer strength of the CS[1:0]#, CKE[1:0] pins. 000 = 0.75X 001 = 1X 010 = 1.25X 011 = 1.5X 100 = 2X 101 = 2.5X 110 = 3X 111 = invalid Default Value=000. 5:3 DQ[63:0], DQM[7:0] Buffer Strength. This field sets the buffer strength of the DQ[63:0], DQM[7:0] pins. 000 = 0.75X 001 = 1X 010 = 1.25X 011 = 1.5X 100 = 2X
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101 = 2.5X 110 = 3X 111 = invalid Default Value=000. 2:0 MA[12:0], BA[1:0], RAS#, CAS#, WE# Buffer Strength. This field sets the buffer strength of the MA[12:0], BA[1:0], RAS#, CAS#, WE# pins. 000 = 0.75X 001 = 1X 010 = 1.25X 011 = 1.5X 100 = 2X 101 = 2.5X 110 = 3X 111 = invalid Default Value=000.
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4.5.2
HOST-AGP Bridge Registers - Device #1
Table 23 summarizes the GMCH-M configuration space for device #1.
Table 23. Host-AGP Bridge Configuration Space (Device #1)
Address Offset 00-01h 02-03h 04-05h 06-07h 08 09 0Ah 0Bh+ 0Ch 0Dh 0Eh 0F-17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1E-1Fh 20-21h 22-23h 24-25h 26-27h 28-3Dh 3Eh 3Fh 40h 41-FFh Register Symbol VID1 DID1 PCICMD1 PCISTS1 RID1 SUBC1 BCC1 MLT1 HDR1 PBUSN SBUSN SUBUSN SMLT IOBASE IOLIMIT SSTS MBASE MLIMIT PMBASE PMLIMIT BCTRL ERRCMD1 Register Name Vendor Identification Device Identification PCI Command Register PCI Status Register Revision Identification Intel Reserved Sub-Class Code Base Class Code Intel Reserved Master Latency Timer Header Type Intel Reserved Primary Bus Number Secondary Bus Number Subordinate Bus Number Secondary Bus Master Latency Timer I/O Base Address Register I/O Limit Address Register Secondary Status Register Memory Base Address Register Memory Limit Address Register Prefetchable Memory Base Address Reg. Prefetchable Memory Limit Address Reg. Intel Reserved Bridge Control Register Intel Reserved Error Command Intel Reserved Default Value 8086h 3576h 0000h 0020h 00h 04h 06h 00h 01h 00h 00h 00h 00h F0h 00h 02A0h FFF0h 0000h FFF0h 0000h 00h 00h Access RO RO RO, R/W RO, R/WC RO RO RO R/W RO RO R/W R/W R/W R/W R/W RO, R/WC R/W R/W R/W R/W R/W R/W -
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4.5.2.1
VID1 - Vendor Identification Register - Device #1
Address Offset: Default Value: Attribute: Size: 00 - 01h 8086h Read Only 16 bits
The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. Default Value=1000/0000/1000/0110.
4.5.2.2
DID1 - Device Identification Register - Device #1
Address Offset: Default Value: Attribute: Size: 02 - 03h 3576h Read Only 16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect.
Bit 15:0
Description Device Identification Number. This is a 16-bit value assigned to the GMCH-M device #1.GMCH-M device #1 DID =3576h. Default Value=0011/0101/0111/0110.
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4.5.2.3
PCICMD1 - PCI-PCI Command Register - Device #1
Address Offset: Default Value: Access: Size 04-05h 0000h Read/Write, Read Only 16 bits
Bit 15:10 9
Descriptions Reserved. Fast Back-to-Back: Not Applicable-hardwired to 0. Default Value=0.
8
SERR Message Enable (SERRE1). This bit is a global enable bit for Device #1 SERR messaging. The GMCH-M does not have an SERR# signal. The GMCH-M communicates the SERR# condition by sending an SERR message to the ICH3-M. If this bit is set to a 1, the GMCH-M is enabled to generate SERR messages over Hub Interface for specific Device #1 error conditions that are individually enabled in the BCTRL register. The error status is reported in the PCISTS1 register. If SERRE1 is reset to 0, then the SERR message is not generated by the GMCH-M for Device #1. NOTE: This bit only controls SERR messaging for the Device #1. Device #0 has its own SERRE bit to control error reporting for error conditions occurring on Device #0. The two control bits are used in a logical OR manner to enable the SERR Hub Interface message mechanism. Default Value=0.
7 6 5 4
Address/Data Stepping: Not applicable. Hardwired to 0. Parity Error Enable (PERRE1): PERR# is not supported on AGP/PCI1. Hardwired to 0. Reserved. Memory Write and Invalidate Enable: (RO) This bit is implemented as Read Only and returns a value of "0" when read. Default Value=0.
3
Special Cycle Enable: (RO) This bit is implemented as Read Only and returns a value of "0" when read. Default Value=0.
2
Bus Master Enable (BME1): (R/W) When the Bus Master Enable is set to "0" (default), AGP Master initiated FRAME# cycles will be ignored by the GMCH-M resulting in a Master Abort. Ignoring incoming cycles on the secondary side of the P2P bridge effectively disables the bus master on the primary side. When Bus Master Enable is set to "1", AGP Master initiated FRAME# cycles will be accepted by the GMCH-M if they hit a valid address decode range This bit has no affect on AGP Master originated SBA or PIPE# cycles. Default Value=0.
1
Memory Access Enable (MAE1): (R/W) This bit must be set to "1" to enable the Memory and Prefetchable memory address ranges defined in the MBASE, MLIMIT, PMBASE, and PMLIMIT registers. When set to "0" all of device #1's memory space is disabled. Default Value=0.
0
I/O Access Enable (IOAE1): (R/W) This bit must be set to "1" to enable the I/O address range defined in the IOBASE, and IOLIMIT registers. When set to "0" all of device #1's I/O space is disabled. Default Value=0.
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PCISTS1 - PCI-PCI Status Register - Device #1
Address Offset: Default Value: Access: Size: 06-07h 0020h Read Only, Read/Write Clear 16 bits
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the "virtual" PCI-PCI bridge embedded within the GMCH-M. Since this device does not physically reside on PCI0 it reports the optimum operating conditions so that it does not restrict the capability of PCI0.
Bit 15 14
Descriptions Detected Parity Error (DPE1): Not Applicable - hardwired to "0". Signaled System Error (SSE1). This bit is set to 1 when GMCH-M Device #1 generates an SERR message over Hub Interface for any enabled Device #1 error condition. Device #1 error conditions are enabled in the PCICMD1 and BCTRL registers. Device #1 error flags are read/reset from the SSTS register. Software clears this bit by writing a 1 to it. Default Value=0.
13 12 11 10:9 8 7 6 5 4:0
Received Master Abort Status (RMAS1): Not Applicable - hardwired to "0". Received Target Abort Status (RTAS1): Not Applicable - hardwired to "0". Signaled Target Abort Status (STAS1): Not Applicable - hardwired to "0". DEVSEL# Timing (DEVT1): Not Applicable - hardwired to "00". Data Parity Detected (DPD1): Not Applicable - hardwired to "0". Fast Back-to-Back (FB2B1): Not Applicable - hardwired to "0". Reserved. 66/60 MHz Capability: Not Applicable - Hardwired to "1". Reserved.
4.5.2.5
RID1 - Revision Identification Register - Device #1
Address Offset: Default Value: Access: Size: 08h 00h Read Only 8 bits
This register contains the revision number of the GMCH-M device #1. These bits are read only and writes to this register have no effect. For the A-0 Stepping, this value is 00h.
Bit 7:0
Description Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the GMCH-M device #1. A-0 Stepping - RID is 00h. Default Value=0000/0000.
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4.5.2.6
SUBC1 - Sub-Class Code Register - Device #1
Address Offset: Default Value: Access: Size: 0Ah 04h Read Only 8 bits
This register contains the Sub-Class Code for the GMCH-M device #1. This code is 04h indicating a PCI-PCI Bridge device. The register is read only.
Bit 7:0
Description Sub-Class Code (SUBC1). This is an 8-bit value that indicates the category of Bridge into which the GMCH-M falls. The code is 04h indicating a Host Bridge. Default Value=0000/0100.
4.5.2.7
BCC1 - Base Class Code Register - Device #1
Address Offset: Default Value: Access: Size: 0Bh 06h Read Only 8 bits
This register contains the Base Class Code of the GMCH-M device #1. This code is 06h indicating a Bridge device. This register is read only.
Bit 7:0
Description Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the GMCH-M device #1. This code has the value 06h, indicating a Bridge device. Default Value=00000110.
4.5.2.8
MLT1 - Master Latency Timer Register - Device #1
Address Offset: Default Value: Access: Size: 0Dh 00h Read/Write 8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a read/write to prevent standard PCI-PCI bridge configuration software from getting "confused".
Bit 7:3
Description Not applicable but support read/write operations. (Reads return previously written data.) Default Value=00000.
2:0
Reserved.
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HDR1 - Header Type Register - Device #1
Address Offset: Default Value: Access: Size: 0Eh 01h Read Only 8 bits
This register identifies the header layout of the configuration space. No physical register exists at this location.
Bit 7:0
Descriptions This read only field always returns 01h when read. Writes have no effect. Default Value=00000001.
4.5.2.10
PBUSN - Primary Bus Number Register - Device #1
Address Offset: Default Value: Access: Size: 18h 00h Read Only 8 bits
This register identifies that "virtual" PCI-PCI bridge is connected to bus #0.
Bit 7:0
Descriptions Bus Number. Hardwired to "0".
4.5.2.11
SBUSN - Secondary Bus Number Register - Device #1
Address Offset: Default Value: Access: Size: 19h 00h Read /Write 8 bits
This register identifies the bus number assigned to the second bus side of the "virtual" PCI-PCI bridge i.e. to PCI1/AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI1/AGP.
Bit 7:0
Descriptions Bus Number. Programmable Default Value=00000000.
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4.5.2.12
SUBUSN - Subordinate Bus Number Register - Device #1
Address Offset: Default Value: Access: Size: 1Ah 00h Read /Write 8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI1/AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI1/AGP.
Bit 7:0
Descriptions Bus Number. Programmable Default Value=00000000.
4.5.2.13
SMLT - Secondary Master Latency Timer Register - Device #1
Address Offset: Default Value: Access: Size: 1Bh 00h Read/Write 8 bits
This register controls the bus tenure of the GMCH-M on AGP/PCI. SMLT is an 8-bit register that controls the amount of time the GMCH-M, as an AGP/PCI bus master, can burst data on the AGP/PCI Bus. The Count Value is an 8-bit quantity, however SMLT[2:0] are reserved and assumed to be 0 when determining the Count Value. The GMCH-M's SMLT is used to guarantee to the AGP master a minimum amount of the system resources. When the GMCH-M begins the first PCI bus cycle after being granted the bus, the counter is loaded and enabled to count from the assertion of FRAME#. If the count expires while the GMCH-M's grant is removed (due to AGP master request), then the GMCH-M will lose the use of the bus, and the AGP master agent may be granted the bus. If GMCH-M's bus grant is not removed, the GMCH-M will continue to own the AGP/PCI bus regardless of the SMLT expiration or idle condition. Note: The GMCH-M must always properly terminate an AGP/PCI transaction, with FRAME# negation prior to the final data transfer. The number of clocks programmed in the SMLT represents the guaranteed time slice (measured in 66MHz PCI clocks) allotted to the GMCH-M, after which it must complete the current data transfer phase and then surrender the bus as soon as its bus grant is removed. For example, if the SMLT is programmed to 18h, then the value is 24 AGP clocks. The default value of SMLT is 00h and disables this function. When the SMLT is disabled, the burst time for the GMCH-M is unlimited (i.e. the GMCH-M can burst forever).
Bit 7:3
Description Secondary MLT counter value. Default Value=00000.
2:0
Reserved.
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IOBASE - I/O Base Address Register - Device #1
Address Offset: Default Value: Access: Size: 1Ch F0h Read/Write 8 bits
This register control the CPU to PCI1/AGP I/O access routing based on the following formula: IO_BASE=< address =Bit 7:4 Description I/O Address Base. Corresponds to A[15:12] of the I/O address. Default Value=1111. 3:0 I/O Addressing Capability. Hardwired to 0h indicating that only 16 bit I/O addressing is supported. Bits [31:16] of the I/O base address is assumed to be 0000h. Default Value=0000.
4.5.2.15
IOLIMIT - I/O Limit Address Register - Device #1
Address Offset: Default Value: Access: Size: 1Dh 00h Read/Write 8 bits
This register controls the CPU to PCI1/AGP I/O access routing based on the following formula: IO_BASE=< address =Bit 7:4
Description I/O Address Limit. Corresponds to A[15:12] of the I/O address. Default Value=0000.
3:0
Reserved. (Only 16 bit addressing supported.)
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4.5.2.16
SSTS - Secondary PCI-PCI Status Register - Device #1
Address Offset: Default Value: Access: Size: 1E-1Fh 02A0h Read Only, Read/Write Clear 16 bits
SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e. PCI1/AGP side) of the "virtual" PCI-PCI bridge embedded within GMCH-M.
Bit 15
Descriptions Detected Parity Error (DPE1). This bit is set to a 1 to indicate GMCH-M's detection of a parity error in the address or data phase of PCI1/AGP bus transactions. Software sets DPE1 to 0 by writing a 1 to this bit. Note that the function of this bit is not affected by the PERRE1 bit. Also note that PERR# is not implemented in the GMCH-M. Default Value=0.
14
Received System Error (SSE1). This bit is hardwired to 0 since the GMCH-M does not have an SERR# signal pin. Default Value=0.
13
Received Master Abort Status (RMAS1). When the GMCH-M terminates a Host-to-PCI1/AGP with an unexpected master abort, this bit is set to 1. Software resets this bit to 0 by writing a 1 to it. Default Value=0.
12
Received Target Abort Status (RTAS1). When a GMCH-M-initiated transaction on PCI1/AGP is terminated with a target abort, RTAS1 is set to 1. Software resets RTAS1 to 0 by writing a 1 to it. Default Value=0.
11
Signaled Target Abort Status (STAS1). STAS1 is hardwired to a 0, since the GMCH-M does not generate target abort on PCI1/AGP. Default Value=0.
10:9
DEVSEL# Timing (DEVT1). This 2-bit field indicates the timing of the DEVSEL# signal when the GMCH-M responds as a target on PCI1/AGP, and is hard-wired to the value 01b (medium) to indicate the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle. Default Value=01.
8
Data Parity Detected (DPD1). Hardwired to 0. GMCH-M does not implement G_PERR# function. However, data parity errors are still detected and reported using SERR Hub Interface special cycles(if enabled by SERRE1 and the BCTRL register, bit 0). Default Value=0.
7
Fast Back-to-Back (FB2B1). This bit is hardwired to 1 since GMCH-M as a target supports fast backto-back transactions on PCI1/AGP. Default Value=1.
6 5 4:0
Reserved. 66/60 MHZ Capability: Hardwired to "1". Reserved.
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MBASE - Memory Base Address Register - Device #1
Address Offset: Default Value: Access: Size: 20-21h FFF0h Read/Write 16 bits
This register controls the CPU to PCI1 non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =Bit 15: 4
Description Memory Address Base (MEM_BASE). Corresponds to A[31:20] of the memory address. Default Value=000000000000.
3:0
Reserved.
4.5.2.18
MLIMIT - Memory Limit Address Register - Device #1
Address Offset: Default Value: Access: Size: 22-23h 0000h Read/Write 16 bits
This register controls the CPU to PCI1 non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =Bit 15: 4
Description Memory Address Limit (MEM_LIMIT). Corresponds to A[31:20] of the memory address. Default Value=000000000000.
3:0
Reserved.
Note:
Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable PCI1/AGP address ranges (typically where control/status memory-mapped I/O data structures of the graphics
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controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address ranges (typically graphics memory). This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved CPU-AGP memory access performance. Note: Configuration software is responsible for programming all address range registers (prefetchable, nonprefetchable) with the values that provide exclusive address ranges i.e. prevent overlap with each other and/or with the ranges covered with the main memory. There is no provision in the GMCH-M hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed.
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PMBASE - Prefetchable Memory Base Address Register - Device #1
Address Offset: Default Value: Access: Size: 24-25h FFF0h Read/Write 16 bits
This register controls the CPU to PCI1 prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE=< address =Bit 15: 4
Description Prefetchable Memory Address Base (PMEM_BASE). Corresponds to A[31:20] of the memory address. Default Value=1111/1111/1111.
3:0
Reserved.
4.5.2.20
PMLIMIT - Prefetchable Memory Limit Address Register - Device #1
Address Offset: Default Value: Access: Size: 26-27h 0000h Read/Write 16 bits
This register controls the CPU to PCI1 prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE=< address =Bit 15: 4
Description Prefetchable Memory Address Limit (PMEM_LIMIT).Corresponds to A[31:20] of the memory address. Default Value=0000/0000/0000.
3:0
Reserved.
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Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e. prefetchable) from the CPU perspective.
4.5.2.21
BCTRL - PCI-PCI Bridge Control Register - Device #1
Address Offset: Default Value: Access: Size 3Eh 00h Read/Write 8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The BCTRL provides additional control for the secondary Interface (i.e. PCI1/AGP) as well as some bits that affect the overall behavior of the "virtual" PCI-PCI bridge embedded within GMCH-M, e.g. VGA compatible address ranges mapping.
Bit 7 6
Descriptions Fast Back-to-Back Enable: Since there is only one target allowed on AGP this bit is meaningless. This bit is hardwired to 0. Secondary Bus Reset: GMCH-M does not support generation of reset via this bit on the AGP and therefore this bit is hardwired to 0. Note that the only way to perform a hard reset of the AGP is via the system reset either initiated by software or hardware via ICH3-M.
5
Master Abort Mode: This bit is hardwired to 0. This means when acting as a master on AGP/PCI1 the GMCH-M will drop writes on the "floor" and return all 1 during reads when a Master Abort occurs. Default Value=0.
4
Reserved.
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Bit 3
Descriptions VGA Enable. Controls the routing of CPU initiated transactions targeting VGA compatible I/O and memory address ranges. When this bit is set, the GMCH-M will forward the following CPU accesses to the AGP: 1) memory accesses in the range 0A0000h to 0BFFFFh 2) I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases - A[15:10] are not decoded) When this bit is set , forwarding of these accesses issued by the CPU is independent of the I/O address and memory address ranges defined by the previously defined base and limit registers. Forwarding of these accesses is also independent of the settings of the bit 2 (ISA Enable) of this register if this bit is 1. If the VGA enable bit is set, then accesses to IO address range x3BCh-x3BFh are forwarded to Hub Interface. If the VGA enable bit is not set then accesses to IO address range x3BCh-x3BFh are treated just like any other IO accesses, i.e. the cycles are forwarded to AGP if the address is within IOBASE and IOLIMIT and ISA enable bit is not set, otherwise they are forwarded to Hub Interface. If this bit is 0, then VGA compatible memory and I/O range accesses are not forwarded to AGP but rather they are mapped to primary PCI unless they are mapped to AGP via I/O and memory range registers defined above (IOBASE, IOLIMIT, MBASE, MLIMIT, PMBASE, PMLIMIT) The following table shows the behavior for all combinations of MDA and VGA: VGA 0 0 1 1 MDA 0 1 0 1 Behavior All References to MDA and VGA Go To Hub Interface (Default) Illegal Combination (DO NOT USE) All References To VGA Go To AGP MDA-only references (I/O Address 3BF and aliases) will go to Hub Interface. VGA References Go To AGP; MDA references go to Hub Interface
Default Value=0. 2 ISA Enable: Modifies the response by the GMCH-M to an I/O access issued by the CPU that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers. When this bit is set to 1, GMCH-M will not forward to PCI1/AGP any I/O transactions addressing the last 768 bytes in each 1KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers. Instead of going to PCI1/AGP these cycles will be forwarded to Hub Interface where they can eventually be subtractive or positively claimed by the ISA bridge. If this bit is "0" (default) then all addresses defined by the IOBASE and IOLIMIT for CPU I/O transactions will be mapped to PCI1/AGP. Default Value=0. 1 0 SERR# Enable. This bit normally controls forwarding SERR# on the secondary interface to the primary interface. The GMCH-M does not support the SERR# signal on the AGP PCI1 bus. Hardwired to a "0". Parity Error Response Enable: Controls GMCH-M's response to data phase parity errors on PCI1/AGP G_PERR# is not implemented by the GMCH-M. However, when this bit is set to 1, address and data parity errors on PCI1 are reported via SERR messaging, if enabled by SERRE1. If this bit is reset to 0, then address and data parity errors on PCI1/AGP are not reported via the GMCH-M SERR# signal. Other types of error conditions can still be signaled via SERR messaging independent of this bit's state. Default Value=0.
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4.5.2.22
ERRCMD1 - Error Command Register - Device #1
Address Offset: Default Value: Access: Size 40h 00h Read/Write 8 bits
Bit 7:1 0
Descriptions Reserved. SERR on Receiving Target Abort on AGP/PCI. When this bit is set to 1 the GMCH-M generates an SERR Hub Interface special cycle when an GMCH-M originated AGP/PCI cycle is terminated with a Target Abort. If this bit is 0, then reporting of this condition is disabled. Default Value=0.
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5.1
Functional Description
System Address Map
An Intel(R) Pentium(R) III Processor-M system based on the 830MP GMCH-M supports 4 GB of addressable memory space and 64 KB+3 of addressable I/O space. (The P6 bus I/O addressability is 64 KB + 3.) There is a programmable memory address space under the 1 MB region that is divided into regions which can be individually controlled with programmable attributes such as Disable, Read/Write, Write Only, or Read Only. The Intel Pentium III Processor-M family supports addressing of memory ranges larger than 4 GB. The GMCH-M claims any CPU access over 4 GB and terminates the transaction without forwarding it to hub interface or AGP. Simply dropping the data terminates writes and for reads the GMCH-M returns all zeros on the host bus. Note that the 830MP platform does not support the PCI Dual Address Cycle Mechanism (DAC) and therefore does not allow addressing of greater than 4 GB on either the hub interface or AGP interface. In the following sections, it is assumed that all of the compatibility memory ranges reside on the hub interface/PCI. The exception to this rule is VGA ranges, which may be mapped to AGP. In the absence of more specific references, cycle descriptions referencing PCI should be interpreted as the hub interface/PCI, while cycle descriptions referencing AGP are related to the AGP bus.
5.1.1
System Memory Address Ranges
The GMCH-M provides a maximum PC133 address decode space of 1.0 GB. The GMCH-M does not re-map APIC memory space. The GMCH-M does not limit SDRAM space in hardware. It is the BIOS or system designer's responsibility to limit SDRAM population so that adequate PCI, AGP, High BIOS, and APIC memory space can be allocated. The following figure represents system memory address map in a simplified form. The following figure provides additional details on mapping specific memory regions as defined and supported by the Intel 830MP chipset.
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Figure 9. Memory System Address Map
4GB
PCI M em ory Address Range
AGP Address Range
(AGP) Aperture
Top of the M ain M emory
M ain M em ory Address Range
Independently Programmable Non-Overlapping M emory Windows
0
GMCH-M Memory Space
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Figure 10. Detailed Memory System Address Map
Extended P6 Memory
AGP Window
Upper BIOS Area (64 KB) AGP Window Lower BIOS Area (64 KB) 16 KB x 4 Expansion Card BIOS and Buffer Area (128 KB) 16 KB x 8
1 MB
960 KB
Pre-Allocated Memory
896 KB
768 KB Standard PCI/ISA Video Memory (SMM Memory) 128 KB Optionally Mapped to AGP
640 KB
Dos Area
5.1.2
Compatibility Area
This area is divided into the following address regions: 0 - 640KB DOS Area 640 - 768KB Video Buffer Area 768 - 896KB in 16-KB sections (total of 8 sections) - Expansion Area 896 -960 KB in 16-KB sections (total of 4 sections) - Extended System BIOS Area 960 KB - 1 MB Memory (BIOS Area) - System BIOS Area There are 16 memory segments in the compatibility area. Thirteen of the memory ranges can be enabled or disabled independently for both read and write cycles.
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Table 24. Memory Segments and Attributes
Memory Segments 000000H - 09FFFFH 0A0000H - 0BFFFFH 0C0000H - 0C3FFFH 0C4000H - 0C7FFFH 0C8000H - 0CBFFFH 0CC000H - 0CFFFFH 0D0000H - 0D3FFFH 0D4000H - 0D7FFFH 0D8000H - 0DBFFFH 0DC000H - 0DFFFFH 0E0000H - 0E3FFFH 0E4000H - 0E7FFFH 0E8000H - 0EBFFFH 0EC000H - 0EFFFFH 0F0000H - 0FFFFFH Attributes Fixed - always mapped to main SDRAM Mapped to hub interface, or AGP configurable as SMM space WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE WE RE Comments 0 to 640K - DOS Region Video Buffer (physical SDRAM configurable as SMM space) Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension BIOS Area
5.1.2.1
DOS Area (00000h-9FFFFh)
The DOS area is 640 KB in size and is always mapped to the main memory controlled by the GMCH-M.
5.1.2.2
Legacy VGA Ranges (A0000h-BFFFFh)
The legacy 128-KB VGA memory range A0000h-BFFFFh (Frame Buffer) can be mapped to AGP/PCI1 (Device #1) and/or to the hub interface depending on the programming of the VGA steering bits. Priority for VGA mapping is constant in that the GMCH-M always decodes internally mapped devices first. The GMCH-M always positively decodes internally mapped device, namely AGP/PCI1. Subsequent decoding of regions mapped to AGP/PCI1or the hub interface depends on the Legacy VGA configurations bits (VGA Enable and MDAP). This region is also the default for SMM space.
5.1.2.3
Compatible SMRAM Address Range (A0000h-BFFFFh)
When compatible SMM space is enabled, SMM-mode CPU accesses to this range are routed to physical system SDRAM at this address. Non-SMM-mode CPU accesses to this range are considered to be to the Video Buffer Area as described above. AGP and hub interface originated cycles to enabled SMM space are not allowed and are considered to be to the Video Buffer Area.
5.1.2.4
Monochrome Adapter (MDA) Range (B0000h - B7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the system. Accesses in the VGA range are forwarded to AGP/PCI1 and the hub interface (depending on
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configuration bits). Since the monochrome adapter may be mapped to anyone of these devices, the GMCH-M must decode cycles in the MDA range and forward them either to, AGP/PCI1 or to the hub interface. This capability is controlled by a VGA steering bits and the legacy configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the GMCH-M decodes IO cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3Bah, and 3BFh and forwards them to the AGP/PCI1 and/or the hub interface.
5.1.2.5
Expansion Area (C0000h-DFFFFh)
This 128-KB ISA Expansion region is divided into eight 16- KB segments. Each segment can be assigned one of four Read/Write states: read-only, write-only, read/write, or disabled. Typically, these blocks are mapped through GMCH-M and are subtractively decoded to ISA space. Memory that is disabled is not remapped.
5.1.2.6
Extended System BIOS Area (E0000h-EFFFFh)
This 64-KB area is divided into four 16-KB segments. Each segment can be assigned independent read and write attributes so it can be mapped either to main SDRAM or to hub interface. Typically, this area is used for RAM or ROM. Memory segments that are disabled are not remapped elsewhere.
5.1.2.7
System BIOS Area (F0000h-FFFFFh)
This area is a single 64-KB segment. This segment can be assigned read and write attributes. It is by default (after reset) Read/Write disabled and cycles are forwarded to hub interface. By manipulating the Read/Write attributes, the GMCH-M can "shadow" BIOS into the main SDRAM. When disabled, this segment is not remapped.
5.1.3
Extended Memory Area
This memory area covers 100000h (1 MB) to FFFFFFFFh (4 GB-1) address range and it is divided into the following regions: Main System SDRAM Memory from 1 MB to the Top of Memory; maximum of 1.0 GB. AGP or PCI Memory space from the Top of Memory to 4 GB with two specific ranges: APIC Configuration Space from FEC0_0000h (4 GB-20 MB) to FECF_FFFFh and FEE0_0000h to FEEF_FFFFh High BIOS area from 4 GB to 4 GB - 2 MB
5.1.3.1
Main System SDRAM Address Range (0010_0000h to Top of Main Memory)
The address range from 1 MB to the top of main memory is mapped to main SDRAM address range controlled by the GMCH-M. The Top of Memory (TOM) is limited to 1.0 GB. All accesses to addresses within this range will be forwarded by the GMCH-M to the SDRAM unless a hole in this range is created using the fixed hole as controlled by the FDHC register. Accesses within this hole are forwarded to hub interface. The GMCH-M provides a maximum SDRAM address decode space of 4 GB. The GMCH-M does not re-map APIC memory space. The GMCH-M does not limit SDRAM address space in hardware. It is the
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BIOS or system designer's responsibility to limit SDRAM population so that adequate PCI, AGP, High BIOS, and APIC memory space can be allocated.
5.1.3.1.1
15 MB-16 MB Window
A hole can be created at 15 MB-16 MB as controlled by the fixed hole enable (FDHC register) in Device 0 space. Accesses within this hole are forwarded to the hub interface. The range of physical SDRAM memory disabled by opening the hole is not remapped to the Top of the memory - that physical SDRAM space is not accessible. This 15 MB-16 MB hole is an optionally enabled ISA hole. Video accelerators originally used this hole. Validation and customer SV teams also use it for some of their test cards. That is why it is being supported. There is no inherent BIOS request for the 15-16 hole.
5.1.3.1.2
Pre-allocated Memory
Physical addresses that are not accessible as general system memory and reside within system memory address range (less than TOM) are created for SMM-mode and legacy VGA graphics compatibility. The Intel 830MP supports an increased amount of pre-allocated memory to support up to 1600X1200X32bpp. The pre-allocated memory allows sizes of 512 KB, 1 MB, or 8 MB. For VGA graphics compatibility, pre-allocated memory is only required in non-local memory configurations. The system BIOS must properly initialize these regions.
5.1.3.2
Extended SMRAM Address Range (HSEG and TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended memory area.
5.1.3.2.1
HSEG
SMM-mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non-SMMmode CPU accesses to enabled HSEG are considered invalid and are terminated immediately on the host interface. The exceptions to this rule are Non-SMM-mode Write Back cycles that are remapped to SMM space to maintain cache coherency. AGP and hub interface originated cycles to enabled SMM space are not allowed. Physical SDRAM behind the HSEG transaction address is not remapped and is not accessible.
5.1.3.2.2
TSEG
TSEG can be up to 1 MB in size and is at the top of physical memory. SMM-mode CPU accesses to enabled TSEG access the physical SDRAM at the same address. Non-SMM-mode CPU accesses to enabled TSEG is considered invalid and are terminated immediately on the host interface. The exceptions to this rule are Non-SMM-mode Write Back cycles that are directed to the physical SMM space to maintain cache coherency. AGP and hub interface originated cycles to enabled SMM space are not allowed. The size of the SMRAM space is determined by the USMM value in the SMRAM register. When the extended SMRAM space is enabled, non-SMM CPU accesses and all other accesses in this range are forwarded to the hub interface. When SMM is enabled the amount of memory available to the system is equal to the amount of physical SDRAM minus the value in the TSEG register.
5.1.3.3
PCI Memory Address Range (Top of Main Memory to 4 GB)
The address range from the top of main SDRAM to 4 GB (top of physical memory space supported by the GMCH-M) is normally mapped via the hub interface to PCI.
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As an AGP configuration, there are two exceptions to this rule. 1. Addresses decoded to the AGP Memory Window defined by the MBASE, MLIMIT, PMBASE, and PMLIMIT registers are mapped to AGP. 2. Addresses decoded to the Graphics Aperture range defined by the APBASE and APSIZE registers are mapped to the main SDRAM. There are two sub-ranges within the PCI Memory address range defined as APIC Configuration Space and High BIOS Address Range. The AGP memory window and AGP Graphics Aperture Window MUST NOT overlap with these two ranges. These ranges are described in detail in the following paragraphs.
5.1.3.4
Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000hFEEF_FFFFh)
This range is reserved for APIC configuration space that includes the default I/O APIC configuration space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh. CPU accesses to the Local APIC configuration space do not result in external bus activity since the Local APIC configuration space is internal to the CPU. However, an MTRR must be programmed to make the Local APIC range uncacheable (UC). The Local APIC base address in each CPU should be relocated to the FEC0_0000h (4 GB-20 MB) to FECF_FFFFh range so that one MTRR can be programmed to 64 KB for the Local and I/O APICs. The I/O APIC(s) usually resides in the ICH3-M portion of the chip-set or as a stand-alone component(s). I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC will be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where x is I/O APIC unit number 0 through F(hex). This address range will be normally mapped to hub interface.
Note:
There is no provision to support an I/O APIC device on AGP. The address range between the APIC configuration space and the High BIOS (FED0_0000h to FFDF_FFFFh) is always mapped to the hub interface.
5.1.3.5
High BIOS Area (FFE0_0000h -FFFF_FFFFh)
The top 2 MB of the Extended Memory Region is reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system BIOS. CPU begins execution from the High BIOS after reset. This region is mapped to hub interface so that the upper subset of this region aliases to 16 MB-256 KB range. The actual address space required for the BIOS is less than 2 MB but the minimum CPU MTRR range for this region is 2 MB so that full 2 MB must be considered.
5.1.4
AGP Memory Address Ranges
The GMCH-M can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in GMCH-M's Device #1 configuration space. The first range is controlled via the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers. The second range is controlled via the Prefetchable Memory Base (PMBASE) and Prefetchable Memory Limit (PMLIMIT) registers Conceptually, address decoding for each range follows the same basic concept. The top 12 bits of the respective Memory Base and Memory Limit registers correspond to address bits A[31:20] of a memory address . For the purpose of address decoding, the GMCH-M assumes that address bits A[19:0] of the memory base are zero and that address bits A[19:0] of the memory limit address are FFFFFh. This
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forces each memory address range to be aligned to 1-MB boundary and to have a size granularity of 1 MB. The GMCH-M positively decodes memory accesses to AGP memory address space as defined by the following equations: Memory_Base_Address * Address * Memory_Limit_Address Prefetchable_Memory_Base_Address * Address * Prefetchable_Memory_Limit_Address The window size is programmed by the plug-and-play configuration software. The window size depends on the size of memory claimed by the AGP device. Normally these ranges will reside above the Top-of-Main-SDRAM and below High BIOS and APIC address ranges. They normally reside above the top of memory (TOM) so they do not steal any physical SDRAM memory space. It is essential to support a separate Prefetchable range in order to apply USWC attribute (from the processor point of view) to that range. The USWC attribute is used by the processor for write combining. Note that the GMCH-M Device #1 memory range registers described above are used to allocate memory address space for any devices sitting on AGP that requires such a window. These devices would include the AGP device, PCI-66 MHz/1.5V agents, and multifunctional AGP devices where one or more functions are implemented as PCI devices. The PCICMD1 register can override the routing of memory accesses to AGP. In other words, the memory access enable bit must be set in the device 1, PCICMD1 register, to enable the memory base/limit and prefetchable base/limit windows.
5.2
5.2.1
Host Interface
Overview
The GMCH-M is optimized for the Intel Pentium III Processor-M. The GMCH-M supports a PSB frequency of 133 MHz using 1.25V AGTL+ signaling. The AGTL+ buffers support single-ended termination. The GMCH-M supports 32-bit host addressing, decoding up to 4 GB of memory address space for the processor. CPU memory writes to address space above 4 GB will be immediately terminated and discarded. CPU memory reads to address space above 4 GB will be immediately terminated and will return the value of the pulled-up GTL host bus. Host initiated I/O cycles are decoded to AGP/PCI1, hub interface, or GMCH-M configuration space. Host initiated memory cycles are decoded to AGP/PCI1, hub interface, or system SDRAM. Host cycles to AGP/PCI or hub interface, are subject to dynamic deferring. All memory accesses from the Host that hit the graphics aperture are translated using an AGP address translation table. GMCH-M accesses to AGP/PCI1 device accesses to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated from AGP/PCI1 using PCI semantics, cacheable accesses from hub interface to SDRAM will be snooped on the host bus.
5.2.2
Intel Pentium III Processor-M Unique PSB Activity
The GMCH-M recognizes and supports a large subset of the transaction types that are defined for the P6 bus interface. However, each of these transaction types has a multitude of response types, some of which are not supported by this controller. All transactions are processed in the order that they are received on the host bus. A summary of transactions supported by the GMCH-M is given in the following table.
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Table 25. Host Bus Transactions Supported by GMCH-M
Transaction Deferred Reply Reserved Interrupt Acknowledge Special Transactions Reserved Reserved Branch Trace Message Reserved Reserved Reserved I/O Read REQa[4:0]# 00000 00001 01000 01000 01000 01000 01001 01001 01001 01001 10000 REQb[4:0]# XXXXX XXXXX 00000 00001 0001x 001xx 00000 00001 0001x 001xx 0 0 x LEN# GMCH-M Support The GMCH-M will initiate a deferred reply for a previously deferred transaction. Reserved Interrupt acknowledge cycles are forwarded to the hub interface bus. See Table 27 in Special Cycles section. Reserved Reserved The GMCH-M will terminate a branch trace message without latching data. Reserved Reserved Reserved I/O read cycles are forwarded to hub interface or AGP/PCI unless they target the GMCH-M configuration space. In this case, the GMCH-M picks up the transaction. I/O write cycles are forwarded to hub interface or AGP/PCI unless they target the GMCH-M configuration space. In this case, the GMCH-M picks up the transaction. Reserved Host initiated memory read and invalidate cycles are forwarded to system SDRAM, hub interface, AGP/PCI, Graphics RDRAM, or Graphics Memory Mapped Registers. The GMCH-M will initiate an MRI (LEN=0) cycle to snoop a hub interface or AGP/PCI, to system SDRAM. Reserved Memory code read cycles are forwarded to system SDRAM, hub interface, or AGP/PCI. Host initiated memory read cycles are forwarded to system SDRAM, hub interface, AGP/PCI, Graphics RDRAM or Graphics Memory Mapped Registers. The GMCH-M will initiate a memory read cycle to snoop a hub interface, or AGP/PCI to system SDRAM. This memory write is a writeback cycle and cannot be retried. The GMCH-M will forward the write to system SDRAM. The memory write cycle will be forwarded to system SDRAM, hub interface, AGP/PCI, or Graphics Memory Mapped Registers.
I/O Write
10001
0 0 x LEN#
Reserved Memory Read & Invalidate
1100x 00010
00xxx 0 0 x LEN#
Reserved Memory Code Read Memory Data Read
00011 00100 00110
0 0 x LEN# 0 0 x LEN# 0 0 x LEN#
Memory Write (no retry) Memory Write (can be retried)
00101
0 0 x LEN#
00111
0 0 x LEN#
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1. 2. 3.
For Memory cycles, REQa[4:3]# = ASZ#. The GMCH-M only supports ASZ# = 00 (32 bit address). REQb[4:3]# = DSZ#. For the Pentium Pro processor, DSZ# = 00 (64 bit data bus size). LEN# = data transfer length as follows: LEN# Data length 00 01 <= 8 bytes (BE[7:0]# specify granularity) Length = 16 bytes BE[7:0]# all active Length = 32 bytes BE[7:0]# all active
4.
10 Reserved.
Table 26. Host Bus Responses Supported by GMCH-M
RS2# 0 0 RS1# 0 0 RS0# 0 1 Description Idle Retry Response This response is generated if an access is to a resource that cannot be accessed by the processor at this time and the logic must avoid deadlock. Hub Interface directed reads and writes, SDRAM locked reads, and AGP/PCI, can be retried. Unless there is an attempt to establish LOCK, the GMCH-M will never Retry a cycle that targets system memory. This response can be returned for all transactions that can be executed `out of order.' Hub Interface directed reads (memory, I/O and Interrupt Acknowledge) and writes (I/O only), AGP/PCI directed reads (memory and I/O) and writes (I/O only), and writes (I/O only) can be deferred. Unless there is an attempt to establish LOCK, the GMCHM will never Defer a cycle that targets system memory. Reserved Not supported This is for transactions where the data has already been transferred or for transactions where no data is transferred. Writes and zero length reads receive this response. This response is given for those transactions where the initial transactions snoop hits on a modified cache line. This response is for transactions where data accompanies the response phase. Reads receive this response. GMCH-M Support
0
1
0
Deferred Response
0 1 1
1 0 0
1 0 1
Reserved Hard Failure No Data Response
1 1
1 1
0 1
Implicit Writeback Normal Data Response
5.2.3
Host Addresses Above 4 GB
CPU memory writes to address space above 4 GB will be terminated and discarded immediately. CPU memory reads to address space above 4 GB will also be immediately terminated and will return the value of the pulled-up GTL host bus.
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5.2.4
Host Bus Cycles
The following transaction descriptions illustrate the various operations in their most straightforward representation. The diagrams do not attempt to show the transaction phase relationships when multiple transactions are active on the CPU bus. For a full description of the CPU Bus functionality please refer to the P6 External Bus Specification, Revision 3.0 and Addendum to P6 External Bus Specification Rev 3.1.
5.2.4.1
Partial Reads
Partial Read transactions include: I/O reads and memory read operations of less than or equal to eight bytes (four consecutive bytes for I/O) within an aligned 8-byte span. The byte enable signals, BE#[7:0], select which bytes in the span to read.
5.2.4.2
Part-Line Read and Write Transactions
The GMCH-M does not support a part-line, i.e. 16-byte transactions.
5.2.4.3
Cache Line Reads
A read of a full cache line (as indicated by the LEN[1:0]=10 during request phase) requires 32 bytes of data to be transferred, which translates into four data transfers for a given request. If selected as a target, the GMCH-M will determine if the address is directed to system SDRAM, hub interface, or AGP/PCI, and provide the corresponding command and control to complete the transaction.
5.2.4.4
Partial Writes
Partial Write transactions include: I/O and memory write operations of eight bytes or less (maximum of four bytes for I/O) within an aligned 8-byte span. The byte enable signals, BE#[7:0], select which bytes in the span to write. I/O writes crossing a 4-byte boundary are broken into two separate transactions by the CPU.
5.2.4.5
Cache Line Writes
A write of a full cache line requires 32 bytes of data to be transferred, which translates into four data transfers for a given request.
5.2.4.6
Memory Read and Invalidate (Length > 0)
A Memory Read and Invalidate (MRI) transaction is functionally equivalent to a cache line read. The purpose this special transaction is to support write allocation (write miss case) of cache lines in the processors. When a processor issues an MRI, the cache line is read as in a normal cache line read operation; however, all other caching agents must invalidate this line if they have it in a shared or exclusive state. If a caching agent has this line in the Modified State, then it must be written back to memory and invalidated. The GMCH-M snarfs the write-back data.
5.2.4.7
Memory Read and Invalidate (Length = 0)
A Memory Read and Invalidate transaction of length zero, MRI(0) does not have an associated Data Response. Executing the transaction will inform other agents in the system that the agent issuing this request wants exclusive ownership of a cache line that is in the Shared State (write hit to a shared line).
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Agents with this cache line will invalidate the line. If this line is in the modified state an implicit writeback cycle is generated and the GMCH-M snarfs the data. The GMCH-M generates length=0 Memory Read and Invalidate transactions for hub interface or AGP/PCI.
5.2.4.8
Memory Read (Length = 0)
A Memory Read of length zero, MR(0), does not have an associated Data Response. This transaction is used by the GMCH-M to snoop for the hub interface to system SDRAM, and AGP/PCI snoopable system SDRAM read accesses. The GMCH-M snoop request policy is identical for hub interface and AGP/PCI transactions. Note that the GMCH-M will perform single MR(0) cycles for hub interface reads less than or equal to 32 bytes, for AGP/PCI master reads or read lines directed to System SDRAM The GMCH-M will do multiple snoop ahead cycles for hub interface burst reads greater than 32 bytes and for AGP/PCI master burst reads (i.e. memory read multiple) to SDRAM.
5.2.4.9
Host Initiated Zero-Length R/W Cycles
Streaming SIMD Extension (SSE) new instructions can result in zero-length read and write cycles to the chipset. The GMCH-M supports a zero-length processor write cycle by executing a 1 QW write cycle to the targeted destination with all 8 byte enables turned off. The following destinations for host initiated zerolength writes are supported: 1. Coherent system memory 2. Aperture mapped to system memory 3. Aperture mapped to graphics memory 4. GMCH-M internal memory-mapped I/O registers 5. PCI (via hub Interface) 6. AGP The GMCH-M only supports zero-length processor read cycles that target coherent system memory or AGP/PCI1. When targeting coherent system memory, the GMCH-M forwards the cycle as a 1 QW read from system SDRAM. The data is returned to the GMCH-M. The GMCH-M then returns a "no data" response to the host and empties the returned data from its buffer.
5.2.4.10
Cache Coherency Cycles
The GMCH-M generates an implicit writeback response during host bus read and write transactions when a CPU asserts HITM# during the snoop phase. The CPU initiated write case has two data transfers, the requesting agents data followed by the snooping agents writeback data. The GMCH-M will perform a memory read and invalidate cycle of length = 0 (MRI[0]) on the CPU bus when a hub interface or AGP/PCI occurs. The GMCH-M will perform a memory read cycle with length = 0 (MR[0]) on the CPU bus when a hub interface or AGP/PCI occurs.
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5.2.4.11
Interrupt Acknowledge Cycles
A processor agent issues an Interrupt Acknowledge cycle in response to an interrupt from an 8259compatible interrupt controller. The Interrupt Acknowledge cycle is similar to a partial read transaction, except that the address bus does not contain a valid address. Interrupt Acknowledge cycle is always directed to the hub interface (never to AGP/PCI).
5.2.4.12
Locked Cycles
The GMCH-M supports resource locking due to the assertion of the LOCK# line on the CPU bus as follows.
5.2.4.12.1
CPU<->System SDRAM Locked Cycles
The GMCH-M supports CPU to SDRAM locked cycles. The host bus may not execute any other transactions until the locked cycle is complete. The GMCH-M arbiter may grant another hub interface or AGP device, but any "Coherent" cycles to SDRAM will be blocked. CPU Lock operations DO NOT block any "Non_Coherent" accesses to SDRAM.
5.2.4.12.2
CPU<->Hub Interface Locked Cycles
Any CPU-to-hub interface locked transaction will initiate a hub interface locked sequence. The P6 bus implements the bus lock mechanism, which means that no change of bus ownership can occur from the time one agent, has established a locked transaction (i.e., the initial read cycle of a locked transaction has completed) until the locked transaction is completed. Note that for CPU-to-hub interface lock transactions, a bit in the request packet indicates a lock transaction. Any concurrent cycle that requires snooping on the host bus is not processed while a LOCK transaction is occurring on the host bus. Hub interface-to-SDRAM locked cycles are not supported.
5.2.4.12.3
CPU<->AGP/PCI Locked Cycles
The AGP/PCI1 interface does not support locked operations and therefore both CPU locked and nonlocked transactions destined to AGP/PCI1 are propagated in the same manner. However, note that any concurrent cycle that requires snooping on the host bus is not processed while a LOCK transaction is occurring on the host bus.
5.2.4.13
Branch Trace Cycles
An agent issues a Branch Trace Cycle for taken branches if execution tracing is enabled. Address Aa[35:3]# is reserved and can be driven to any value. D[63:32]# carries the linear address of the instruction causing the branch and D[31:0]# carries the target linear address. The GMCH-M will respond and retire this transaction but will not latch the value on the data lines or provide any additional support for this type of cycle.
5.2.4.14
Special Cycles
A Special Cycle is defined when REQa[4:0] = 01000 and REQb[4:0]= xx001. In the first address phase Aa[35:3]# is undefined and can be driven to any value. In the second address phase, Ab[15:8]# defines
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the type of Special Cycle issued by the processor. All Host initiated Special Cycles are routed to hub interface. Special Cycles are "posted" into the GMCH-M. The host bus transaction is terminated immediately. It does not wait for the cycle to propagate or terminate on hub interface. Table 27 specifies the cycle type and definition as well as the action taken by the GMCH-M when the corresponding cycles are identified. Note that none of the host bus special cycles are propagated to the AGP interface.
Table 27. GMCH-M Responses to Host Initiated Special Cycles
BE[7:0}# 0000 0000 0000 0001 Special Cycle Type NOP Shutdown Action Taken This transaction has no side effects. This transaction is issued when an agent detects a severe software error that prevents further processing. This cycle is claimed by the GMCH-M and propagated as a Shutdown special cycle over the hub interface bus. This cycle is retired on the CPU bus after the associated hub interface special cycle request packet is successfully broadcast over hub interface. This transaction is issued when an agent has invalidated its internal caches without writing back any modified lines. The GMCH-M claims this cycle and simply retires it. This transaction is issued when an agent executes a HLT instruction and stops program execution. This cycle is claimed by the GMCH-M and propagated over hub interface as a Halt special cycle. This cycle is retired on the CPU bus after the associated hub interface special cycle request packet is successfully broadcast over hub interface. This transaction is issued when an agent has written back all modified lines and has invalidated its internal caches. The GMCH-M claims this cycle and simply retires it. This transaction is issued when an agent has completed a cache sync and flush operation in response to an earlier FLUSH# signal assertion. The GMCH-M claims this cycle and simply retires it. This transaction is issued when an agent enters Stop Clock mode. This cycle is claimed by the GMCH-M and propagated over hub interface as a Stop Grant special cycle. This cycle is retired on the CPU bus after the associated hub interface special cycle request packet is successfully broadcast over hub interface. This transaction is first issued when an agent enters the System Management Mode (SMM). Ab[7]# is also set at this entry point. All subsequent transactions from the CPU with Ab[7]# set are treated by the GMCH-M as accesses to the SMM space. No corresponding cycle is propagated to the hub interface. To exit the System Management Mode the CPU issues another one of these cycles with the Ab[7]# bit deasserted. The SMM space access is closed by the GMCH-M at this point.
0000 0010
Flush
0000 0011
Halt
0000 0100
Sync
0000 0101
Flush Acknowledge
0000 0110
Stop Clock Acknowledge
0000 0111
SMI Acknowledge
All others
Reserved
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5.2.5
In-Order Queue Pipelining
All agents on the CPU bus track the number of pipelined bus transaction with an in-order queue (IOQ). The GMCH -M can support an IOQ depth of 8 and uses BNR# to guarantee that limit is not exceeded.
5.2.6
Write Combining
To allow for high speed write capability for graphics, the USWC (uncacheable, speculative, writecombining) memory type provides a write-combining buffering mechanism for write operations. A high percentage of graphics transactions are writes to the memory-mapped graphics region, normally known as the linear frame buffer. Reads and writes to USWC are non-cached and can have no side effects. In the case of graphics, current 32-bit drivers (without modifications) would use Partial Write protocol to update the frame buffer. The highest performance write transaction on the CPU bus is the Line Write. By combining several back-to-back Partial write transactions (internal to the CPU) into a Line write transaction on the CPU bus, the performance of frame buffer accesses would be greatly improved. To this end, the CPU supports the USWC memory. Writes to USWC memory can be buffered and combined in the processor's write-combining buffers (WCB). , or the WCB is full (32 bytes)The WCB can be flushed under different situations*. In order to extend this capability to the current drivers, it is necessary to set up the linear frame buffer address range to be USWC memory type. This can be done by programming the MTRR registers in the CPU. If the number of bytes in the WCB is < 32 then a series of <= 8 byte writes are performed upon WCB flushing. The GMCH-M further optimizes this by providing write combining for CPU-to-hub interface, and CPU-to-AGP/PCI Write transactions. If the target of CPU writes is hub interface memory, then the data is combined and sent to the hub interface bus as a single write burst. The same concept applies to CPU writes to AGP/PCI memory. The USWC writes that target system SDRAM are handled as regular system SDRAM writes. Note that the application of USWC memory attribute is not limited only to the frame buffer support and that the GMCH-M implements write combining for any CPU-to-hub interface or CPU-to-AGP/PCI posted write. *Please refer to the following documents on how to implement write combining buffers: Intel Write Combining Memory Implementation Guidelines (24422) and Intel(R) Architecture Software Developer's Manual Volume 3 System Programming Guide (245572)
5.3
5.3.1
System Memory Interface
SDRAM Interface Overview
The Intel 830MP chipset integrates a main memory SDRAM controller with a 64-bit wide interface. 830MP's system memory buffers support LVTTL (SDRAM) signaling at 133 MHz. * Configured for Single Data Rate SDRAM, the Intel 830MP chipset's memory interface includes support for: * Up to 1.0 GB of 133-MHz SDRAM using 512-Mb technology * PC133 SO-DIMMs * Maximum of 2 SO-DIMMs, Single-sided and/or Double-sided * The 830MP chipset only supports 4 bank memory technologies.
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* Four Integrated Clock buffers The 2-bank select lines SM_BA[1:0] and the 13 Address lines SM_MA[12:0] allow 830MP to support 64 bit wide SO-DIMMs using 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAM technology. While address lines SM_MA[9:0] determine the starting address for a burst, burst lengths are fixed at 4. Six chip selects SM_CS# lines allow maximum of three rows of single-sided SO-DIMMs and six rows of double-sided SDRAM SO-DIMMs. The Intel 830MP chipset's main memory controller targets CAS latencies of 2 and 3 for SDRAM. The 830MP chipset provides refresh functionality with programmable rate (normal SDRAM rate is 1 refresh/15.6 ms). For write operations of less than a Qword in size, the Intel 830MP chipset will perform a byte-wise write.
5.3.2
SDRAM Organization and Configuration
In the following discussion the term row refers to a set of memory devices that are simultaneously selected by a SM_CS# signal. 830MP will support a maximum of 4 rows of memory. For the purposes of this discussion, a "side" of a SO-DIMM is equivalent to a "row" of SDRAM devices. The 2-bank select lines SM_BA[1:0] and the 13 Address lines SM_MA[12:0] allow 830MP to support 64-bit wide SO-DIMMs using x16 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAM technologies.
Table 28. System Memory SO-DIMM Configurations
Max Capacity SDR(2 SODIMMs) 128 MB 256 MB 512 MB 1.0 GB Device Depth Device Width Capacity Per Side SDRAM Technology( Density) # of Column Addr Bits Devices Per Side Page Size 2 KB 4 KB 4 KB 8 KB # of Row Addr Bits # of Bank Addr Bits 2 2 2 2
64 Mb 128 Mb 256 Mb 512 Mb
4M 8M 16M 32M
X16 X16 X16 X16
4 4 4 4
32 MB 64 MB 128 MB 256 MB
12 12 13 13
8 9 9 10
5.3.2.1
Configuration Mechanism for SO-DIMMs
Detection of the type of SDRAM installed on the SO-DIMM is supported via Serial Presence Detect mechanism as defined in the JEDEC SO-DIMM specification. This uses the SCL, SDA and SA[2:0] pins on the SO-DIMMs to detect the type and size of the installed SO-DIMMs. No special programmable modes are provided on the Intel 830MP chipset for detecting the size and type of memory installed. Type and size detection must be done via the serial presence detection pins.
5.3.2.1.1
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the Intel 830MPchipset SDRAM registers must be initialized. The Intel 830MP chipset must be configured for operation with the installed memory types. Detection of memory type and size is done via the System Management Bus (SMB) interface on the ICH3-M. This two-wire bus is used to extract the SDRAM type and size information from the serial presence detect port on the SDRAM SO-DIMMs. SDRAM SO-DIMMs contain a 5-pin serial presence detect interface, including SCL (serial clock), SDA (serial data) and SA[2:0]. Devices on the SMBus have a 7-bit address. For the SDRAM SO-DIMMs, the upper 4 bits are fixed at 1010. The
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lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected directly to the System Management Bus on the ICH3-M. Thus data is read from the Serial Presence Detect port on the SODIMMs via a series of IO cycles to the south bridge. BIOS essentially needs to determine the size and type of memory used for each of the rows of memory in order to properly configure the 830MP memory interface.
5.3.2.1.2
SDRAM Register Programming
This section provides an overview of how the required information for programming the SDRAM registers is obtained from the Serial Presence Detect ports on the SO-DIMMs. The Serial Presence Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by row basis), SDRAM Timings, Row Sizes, and Row Page Sizes. The following table lists a subset of the data available through the on board Serial Presence Detect ROM on each SO-DIMM.
Table 29. Data Bytes on SO-DIMM Used for Programming SDRAM Registers
Byte 2 3 4 5 11 12 17 36-41 42 126 Function Memory Type (EDO, SDR SDRAM) # of Row Addresses, not counting Bank Addresses # of Column Addresses # of banks of SDRAM (Single or Double sided SO-DIMM) ECC, no ECC Refresh Rate # Banks on each Device Access Time from Clock for CAS# Latency 1 through 7 Data Width of SDRAM Components Memory Frequency
Table 29 is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes collectively provide enough data for programming the 830MP SDRAM registers
5.3.3
SDRAM Address Translation and Decoding
The Intel 830MP chipset contains address decoders that translate the address received on the host bus, or the hub interface to an effective memory address. Decoding and Translation of these addresses vary with the three SDRAM types. Also, the number of pages, page sizes, and densities supported vary with the 4 SDRAM types. In general, the Intel 830MP chipset supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAM devices. The multiplexed row/column address to the SDRAM memory array is provided by the SM_BA[1:0] and SM_MA[12:0] signals. These addresses are derived from the host address bus as defined by the table above for SDRAM devices.
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Table 30. Address Translation and Decoding
Address Usage Tech Depth Width Row Col Bank Size 1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Row Page BS BS MA MA MA MA MA MA MA MA MA MA MA MA MA
64 Mb
4M
16
12
8
2
32 MB
2K
12 12
11 11
X X
15 X
14 PA
13 X
24 X
23 10
22 9
21 8
20 7
19 6
18 5
17 4
16 3
128 Mb
8M
16
12
9
2
64 MB
4K
13 13
12 12
X X
15 X
14 PA
25 X
24 11
23 10
22 9
21 8
20 7
19 6
18 5
17 4
16 3
256 Mb
16M
16
13
9
2
128 MB
4K
13 13
12 12
15 X
14 X
26 PA
25 X
24 11
23 10
22 9
21 8
20 7
19 6
18 5
17 4
16 3
512 Mb
16M
16
13
10
2
256 MB
8K
14 14
13 13
15 X
27 X
26 PA
25 12
24 11
23 10
22 9
21 8
20 7
19 6
18 5
17 4
16 3
5.3.4
SDRAM Performance Description
The overall SDRAM performance is controlled by the SDRAM timing register, pipelining depth used in the Intel 830MP chipset, SDRAM speed grade, and the type of SDRAM used in the system. Besides this, the exact performance in a system is also dependent on the total memory supported, external buffering and memory array layout. The most important contribution to overall performance by the System Memory controller is to minimize the latency required to initiate and complete requests to memory, and to support the highest possible bandwidth (full streaming, quick turn-arounds). One measure of performance is the total flight time to complete a cache line request. A true discussion of performance really involves the entire chipset, not just the System Memory controller.
5.4
AGP Interface
The GMCH-M will support 1.5V AGP 1x/2x/4x devices. The AGP signal buffers will have one mode of operation; 1.5V drive/receive (not 3.3V tolerant). The GMCH-M will support 4x (266MT/s) clocking transfers for read and write data, and sideband addressing. The GMCH-M has a 32-deep AGP request queue. The GMCH-M integrates a fully associative 16 entry Translation Look-aside Buffer. AGP semantic transactions to system SDRAM do not get snooped and are therefore not coherent with the CPU caches. PCI semantic transactions on AGP to system SDRAM are snooped. AGP semantic accesses to hub interface/PCI are not supported. PCI semantic access from an AGP master to hub interface is not supported.
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5.4.1
AGP Target Operations
As an initiator, the GMCH-M does not initiate cycles using AGP enhanced protocols. The GMCH-M supports AGP target interface to main memory only. The GMCH-M supports interleaved AGP and PCI transactions. The following table summarizes target operation support of GMCH-M for AGP masters.
Table 31. AGP Commands Supported by GMCH-M When Acting as an AGP Target
AGP Command C/BE[3:0]# Encoding Read 0000 0000 Hi-Priority Read 0001 0000 Reserved Reserved Write 0010 0011 0100 0100 Hi-Priority Write 0101 0101 Reserved Reserved Long Read 0110 0111 1000 Cycle Destination Main Memory Hub interface Main Memory hub interface N/A N/A Main Memory hub interface Main Memory hub interface N/A N/A Main Memory Hub interface Hi-Priority Long Read 1001 Main Memory Hub interface Flush Reserved Fence Reserved Reserved Reserved NOTE: 1010 1011 1100 1101 1110 1111 GMCH-M N/A GMCH-M N/A N/A N/A GMCH-M Host Bridge Response as AGP Target Low Priority Read Complete with random data High Priority Read Complete with random data No Response No Response Low Priority Write Cycle goes to SDRAM with BE's inactive High Priority Write Cycle goes to SDRAM with BE's inactive - does not go to hub interface No Response No Response Low Priority Read Complete locally with random data does not go to hub interface High Priority Read Complete with random data Complete with QW of Random Data No Response No Response - Flag inserted in GMCHM request queue No Response No Response No Response
N/A refers to a function that is not applicable.
As a target of an AGP cycle, the GMCH-M supports all the transactions targeted at main memory and summarized in the table above. The GMCH-M supports both normal and high priority read and write requests. The GMCH-M will not support AGP cycles to hub interface. AGP cycles do not require coherency management and all AGP initiator accesses to main memory using AGP protocol are treated as non-snoopable cycles. These accesses are directed to the AGP aperture in main memory that is programmed as either uncacheable (UC) memory or write combining (WC) in the processor's MTRRs.
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5.4.2
AGP Transaction Ordering
The GMCH-M observes transaction ordering rules as defined by the AGP 2.0 specification.
5.4.3
AGP Electricals
4x/2x/1x and PCI data transfers use 1.5V signaling levels as described in the AGP 2.0 specification.
5.4.4
Support for PCI-66 Devices
The GMCH-M's AGP interface may be used as a PCI-66 MHz interface with the following restrictions: * Support for 1.5-V operation only. * Support for only one device. GMCH-M will not provide arbitration or electrical support for more than one PCI-66 device. * The PCI-66 device must meet the AGP 2.0 electrical specification. * The GMCH-M does not provide full PCI-to-PCI bridge support between AGP/PCI and hub interface. Traffic between AGP and hub interface is limited to hub interface-to-AGP memory writes. * LOCK# signal is not present. Neither inbound nor outbound locks are supported. * SERR#/PERR# signals are not present. * 16-clock Subsequent Data Latency timer (instead of 8)
5.4.5
4x AGP Protocol
In addition to the 1x and 2x AGP protocol the GMCH-M supports 4x AGP read and write data transfers, and 4x sideband address generation. 4x operation will be compliant with the 4x AGP spec as currently described in AGP 2.0. The 4x data transfer protocol provides 1.06 GB/s transfer rates. The control signal protocol for the 4x data transfer protocol is identical to 1x/2x protocol. In 4x mode 16 bytes of data are transferred during each 66-MHz clock period. The minimum throttle-able block size remains four 66-MHz clocks which means 64 bytes of data is transferred per block. Three additional signal pins are required to implement the 4x data transfer protocol. These signal pins are complementary data transfer strobes for the AD bus (2) and the SBA bus (1).
5.4.6
Fast Writes
The Fast Write (FW) transaction is from the core logic to the AGP master acting as a PCI target. This type of access is required to pass data/control directly to the AGP master instead of placing the data into main memory and then having the AGP master read the data. For 1x transactions, the protocol simply follows the PCI bus specification. However, for higher speed transactions (2x or 4x), FW transactions will follow a combination for PCI and AGP bus protocols for data movement.
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5.4.7
AGP-to-Memory Read Coherency Mechanism
The Global Write Buffer (GWB) in the 830MP chipset is used to post write data from the CPU, AGP/PCI, and hub interfaces prior to the data actually being written to system SDRAM. Reads to system SDRAM are allowed to pass the writes in the GWB. This policy requires that all reads to SDRAM be checked against the writes in the GWB to maintain data coherency. If an AGP read hits a write in the GWB, that particular write in the GWB and all writes queued in front of it are written to SDRAM prior to the read. After the data hit by the AGP read is written to SDRAM the AGP read cycle is generated to the SDRAM.
5.4.8
PCI Semantic Transactions on AGP
The GMCH-M accepts and generates PCI semantic transactions on the AGP bus. The GMCH-M guarantees that PCI semantic accesses to SDRAM are kept coherent with the CPU caches by generating snoops to the CPU bus.
5.4.8.1
PCI Read Snoop-Ahead and Buffering
The GMCH-M issues snoops dynamically for the various types of memory read transactions and retains the contents of the AGP/PCI-to-SDRAM read buffers between AGP/PCI transactions. For Memory Reads the GMCH-M will issue one snoop and the entire cache line of read data will be buffered. If a Memory Read bursts across the cache line another snoop will be issued. Subsequent Memory Read transaction hitting the cache line buffer will return data from the buffer. For Memory Read Line and Memory Read Multiple the GMCH-M issues two snoops (a snoop followed by a snoop-ahead) on the host bus and releases the CPU bus for other traffic. When the first DW of the first cache line is delivered and FRAME# is still asserted, the GMCH-M will issue another snoop-ahead on the host bus. This allows the GMCH-M to continuously supply data during Memory Read Line and Memory Read Multiple bursts. When the transaction terminates there may be a minimum of 2 cache lines and a maximum of 2 cache line plus 7 Dwords buffered. Subsequent Memory Reads hitting the buffers will return data from the buffer.
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5.4.8.2
GMCH-M Initiator and Target Operations
The following table summarizes target operation support of GMCH-M for AGP/PCI1 bus initiators. The cycles can be either destined to main memory or the hub interface bus.
Table 32. PCI Commands Supported by GMCH-M When Acting as a PCI Target
PCI Command C/BE[3:0]# Encoding Cycle Destination Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read 0000 0001 0010 0011 0100 0101 0110 0110 Memory Write 0111 0111 Reserved Reserved Configuration Read Configuration Write Memory Read Multiple 1000 1001 1010 1011 1100 1100 Dual Address Cycle Memory Read Line 1101 1110 1110 Memory Write and Invalidate 1111 1111 NOTE: N/A refers to a function that is not applicable. N/A N/A N/A N/A N/A N/A Main Memory hub interface Main Memory hub interface N/A N/A N/A N/A Main Memory hub interface N/A Main Memory hub interface Main Memory hub interface GMCH-M Response as PCI Target No Response No Response No Response No Response No Response No Response Read No Response Posts Data No Response No Response No Response No Response No Response Read No Response No Response Read No Response Posts Data No Response
As a target of an AGP/PCI cycle, GMCH-M only supports the following transactions: Memory Read - The GMCH-M will issue one snoop and the entire cache line of read data will be buffered. If a Memory Read bursts across the cache line another snoop will be issued but the transaction will be disconnected on the cache line boundary. Subsequent Memory Read transaction hitting the cache line buffer will return data from the buffer. Memory Read Line, and Memory Read Multiple - These commands are supported identically by the GMCH-M. The GMCH-M issues two snoops (a snoop followed by a snoop-ahead) on the host bus and releases the CPU bus for other traffic. When the first DW of the first cache line is delivered and FRAME# is still asserted, the GMCH-M will issue another snoop-ahead on the host bus. This allows the GMCH-M to continuously supply data during Memory Read
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Line and Memory Read Multiple bursts. When the transaction terminates there may be a minimum of 2 cache lines and a maximum of 2 cache line plus 7 Dwords buffered. Subsequent Memory Reads hitting the buffers will return data from the buffer. Memory Write and Memory Write and Invalidate - These commands are aliased and processed identically. The GMCH-M supports data streaming for PCI-to-SDRAM writes based on its ability to buffer up to 128 bytes (16 Qwords) of data before a snoop cycle must be completed on the host bus. The GMCH-M is typically able to support longer write bursts, with the maximum length dependent upon concurrent host bus traffic during PCI-SDRAM write data streaming. Fast Back-to-Back Transactions - GMCH-M as a target supports fast back-to-back cycles from a PCI initiator. As a PCI initiator the GMCH-M is responsible for translating host cycles to AGP/PCI1 cycles. The GMCH-M also transfers hub interface to AGP/PCI1 write cycles. The following table shows all the cycles that need to be translated.
Table 33. PCI Commands Supported by GMCH-M When Acting as an AGP/PCI1 Initiator
Source Bus Command Other Encoded Information GMCH-M Host Bridge Corresponding PCI1 Command Source Bus: Host Deferred Reply Interrupt Acknowledge Special Cycle Don't Care Length 8 Bytes Shutdown Halt Stop Clock Grant All other combinations Branch Trace Message I/O Read I/O Write I/O Read to 0CFCh I/O Write to 0CFCh None Length 8 Bytes up to 4 BEx asserted Length 8 Bytes up to 4 BEx asserted Length 8 Bytes up to 4 BEx asserted Length 8 Bytes up to 4 BEx asserted Length < 8 Bytes without all BEs asserted Memory Read (Code or Data) Memory Read Invalidate Length = 8 Bytes with all BEs asserted Length = 16 Bytes Length = 32 Bytes Code Only Length < 8 Bytes without all Bes asserted None None None None None None None I/O Read I/O Write Configuration Read Configuration Write Memory Read Memory Read None Memory Read Memory Write N/A N/A N/A N/A N/A N/A N/A 0010 0011 1010 1011 0110 1110 N/A 1110 0111 C/BE[3:0]# Encoding
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Source Bus Command
Other Encoded Information
GMCH-M Host Bridge Corresponding PCI1 Command C/BE[3:0]# Encoding N/A 0111
1
Memory Write
Length = 16 Bytes Length = 32 Bytes
None Memory Write Unlocked Access None None
Locked Access Reserved Encodings EA Memory Access
All combinations All Combinations Address 4 GB
As Applicable N/A N/A
Source Bus: hub interface Memory Write Memory Write 0111 NOTES: 1. CPU to AGP/PCI1 bus can result in deadlocks. Locked access to AGP/PCI1 bus is strongly discouraged. 2. N/A refers to a function that is not applicable. Not Supported refers to a function that is available but specifically not implemented on GMCH-M.
As an initiator of AGP/PCI1 cycle, the GMCH-M only supports the following transactions: Memory Read - All CPU to AGP/PCI1 reads will use the Memory Read command. Memory Write - GMCH-M initiates AGP/PCI1 cycles on behalf of the CPU or hub interface. GMCHM does not issue Memory Write and Invalidate as an initiator. GMCH-M does not support write merging or write collapsing. GMCH-M will combine CPU-to-PCI writes (Dword or Qword) to provide bursting on the AGP/PCI1 bus. GMCH-M allows non-snoopable write transactions from hub interface to the AGP/PCI1 bus. I/O Read and Write - I/O read and write from the CPU are sent to the AGP/PCI1 bus. I/O base and limit address range for PCI1 bus are programmed in AGP/PCI1 configuration registers. All other accesses that do not correspond to this programmed address range are forwarded to hub interface. Exclusive Access - GMCH-M will not issue a locked cycle on AGP/PCI1 bus on the behalf of either the CPU or hub interface. Hub interface and CPU locked transactions to AGP/PCI1 will be initiated as unlocked transactions by the GMCH-M on the AGP/PCI1 bus. Configuration Read and Write - Host Configuration accesses to internal GMCH-M registers are driven onto AGP/PCI1 as Type 1 Configuration Cycles where they are then claimed by the GMCH-M. This is done to support co-pilot mode. Host Configuration cycles to AGP/PCI1 are forwarded as Type 1 Configuration Cycles.
5.4.8.3
GMCH-M Retry/Disconnect Conditions
The GMCH-M generates retry/disconnect according to the AGP Specification rules when being accessed as a target from the AGP interface (using PCI semantics).
5.4.8.4
Delayed Transaction
When an AGP/PCI-to-SDRAM read cycle is retried by the GMCH-M it will be processed internally as a Delayed Transaction. The GMCH-M supports the Delayed Transaction mechanism on the AGP target interface for the transactions issued using PCI semantics. This mechanism is compatible with the PCI 2.2 Specification.
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The process of latching all information required to complete the transaction, terminating with Retry, and completing the request without holding the master in wait-states is called a Delayed Transaction. The GMCH-M latches the Address and Command when establishing a Delayed Transaction. The GMCH-M generates a Delayed Transaction on the AGP only for SDRAM read accesses.
5.5
GMCH-M Power and Thermal Management
The following list provides the GMCH-M Power and Thermal Management Features: * ACPI 1.0b & 2.0 support * Mobile Power Reduction operating modes (C3, S1) * System States: S0, S1, S3, S4, S5 * CPU States: C0, C1, C2, C3 * Compatible with Intel 815EM AGP Busy/Stop protocol * Intel SpeedStep technology support * Thermal Throttling for Main memory
5.5.1
ACPI 2.0 Support
Advanced Configuration and Power Management Interface (ACPI) primarily describes and runs motherboard devices. It is completely controlled by the operating system that OS drivers directly power down PCI/AGP devices. System or SMI BIOS plays a part of waking the system, however. Device drivers save and restore state while bus drivers change the physical power state of the device. The GMCH-M power management architecture is designed to allow single systems to support multiple suspend modes and to switch between those modes as required. A suspended system can be resumed via a number of different events. The system returns to full operation where it can continue processing or be placed into another suspend mode (potentially a lower power mode than it resumed from). GMCH-M supports the minimum requirements for ACPI support. GMCH-M must support the minimum requirements for both system logic and for graphics controllers, as well as be capable of controlling monitors minimum functions. The transition sequences of entering and exiting system, CPU and graphics states are described in respective sections below.
5.5.2
ACPI States Supported
The Intel 830MP chipset supports the following ACPI States: 1. System States G0/S0 G1/S1 G1/S3 G1/S4 G2/S5 Full On Power On Suspend (POS). System Context Preserved. Suspend to RAM (STR). Power and context lost to chipset. Suspend to Disk (STD). All power lost (except wakeup on ICH3-M) Hard off. Total reboot.
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2.
CPU States C0 C1 C2 Desktop C2 Mobile C3 Full On Auto Halt Stop Grant; Clock to CPU still running. Clock stopped to CPU core. Quick Start (lower power than Stop Grant). Deep Sleep. Clock to CPU stopped.
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5.5.3
Intel 830MP Chipset System and CPU States
Table 34 shows the state combinations that 830MP supports.
Table 34. Intel 830MP Chipset System and CPU States
Global (G) State G0 G0 G0 Sleep (S) State S0 S0 S0 CPU (C) State C0 C1 C2 Processor State Full On Auto-Halt Quick Start (M) Stop Grant (DT) G0 G1 G1 G1 G2 G3 S0 S1 S3 S4 S5 NA C3 C3 Power off Power off Power off Power off Deep Sleep Deep Sleep Power off Power off Power off Power off Description Full On Auto Halt Quick Start Stop grant Deep Sleep Power On Suspend Suspend to RAM Suspend to Disk Hard Off. Mechanical Off.
5.5.4
5.5.4.1
Intel 830MP Chipset CPU "C" States
Full-On (C0)
This is the only state that runs software. All clocks are running, STPCLK# is deasserted and the processor core is active. The processor can service snoops and maintain cache coherency in this state.
5.5.4.2
Auto-Halt (C1)
The first level of power reduction occurs when the processor executes an Auto-Halt instruction. This stops the execution of the instruction stream and greatly reduces the processors power consumption. The processor can service snoops and maintain cache coherency in this state.
5.5.4.3
Quickstart (C2)
The next level of power reduction occurs when the processor is placed into the Quick start state by the assertion of STPCLK#. Mobile Quickstart state is a lower power version of the desktop Stop Grant state. The processor can service snoops and maintain cache coherency in this state. The system can transition from the C0 state to the C2 state for several reasons. Software. C2 is entered when software reads the Level 2 Register. This is an ACPI defined register but BIOS or APM (via BIOS) can use this facility when entering a low power state. Throttling. This function can be enabled or disabled via a configuration bit. When this function is enabled STPCLK# will be asserted to place the processor into the C2 state with a programmable duty cycle. This is an ACPI defined function but BIOS or APM (via BIOS) can use this facility.
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Thermal Override. The chipset will detect thermal events via an input to the ICH3-M. When a thermal threshold has been exceeded a thermal sensor will assert a signal to the ICH3-M. If the signal remains asserted for more than 2 seconds the chipset will initiate thermal throttling. STPCLK# will be asserted to place the processor into the C2 state with a programmable duty cycle. This function can be enabled or disabled via a configuration bit. The Thermal Override condition is handled by the ICH3-M.
5.5.4.4
Deep Sleep (C3)
The Deep Sleep and Deeper Sleep states are identical as far as the GMCH-M is concerned. The only difference externally is that the CPU voltage is lowered for Deeper Sleep state to a point where the CPU will no longer operate, but it will retain its state. It uses a new power savings mode in the mobile Intel Pentium III Processor-M. The C3 entry and exit sequence is also followed by an Intel SpeedStep transition. C3 entry will generally occur when the system is idle, and no bus master activity has taken place recently as indicated by PCI REQ# signals and AGP_BUSY# (although AGP_BUSY# being active does not guarantee C3 will not be entered). Intel SpeedStep transitions may occur at any time, while the system is busy and bus master activity is occurring. There will be no attempt to wait for the system to be idle for an Intel SpeedStep transition. C3 may be entered even if AGP_BUSY# is active, since there is a delay from the time AGP_BUSY# is sampled by the OS and C3 is actually entered. AGP_BUSY# does not prevent C3 entry in hardware, it only indicates to the OS that activity is present. The OS will choose C2 rather than C3 in this case. AGP_BUSY# active will cause a C3 exit, however, so the C3 mode will be brief if AGP_BUSY# is active. An Intel SpeedStep transition, which appears to the GMCH-M exactly as a C3 entry/exit, will occur regardless of the state of AGP_BUSY# The GMCH-M can assume that no AGP, AGP/PCI, or Hub Interface cycle (except special cycles) will occur while the GMCH-M is in the C3 state. The processor cannot snoop its caches to maintain coherency while in the C3 state.
5.5.5
Intel 830MP Chipset AGP_BUSY# Protocol with External Graphics
The AGP_BUSY# and STP_AGP# signals allow power management signaling between an external AGP graphics controller and the ICH3-M. AGP_BUSY# indicates that the AGP device is busy. C3_STAT# (STP_AGP#) is the signal, which used for indicating to the AGP device that a C3 state transition is beginning or ending. AGP_BUSY# (ICH3-M signal) and STP_AGP# (AGP graphics controller signal) are not directly connected to the GMCH-M. For proper implementations, please consult Intel Field Application Engineers
5.5.6
Intel SpeedStep Technology
Intel SpeedStep technology allows the system to operate in multiple performance states Intel SpeedStep technology define two CPU/system operational modes: MaximumPerformance Mode: Maximum CPU Core Frequency, requiring a higher CPU Core voltage. Battery Optimized Mode: Reduced CPU core frequency to extend battery life. Allows for lower CPU Core voltage for additional power savings. Intel SpeedStep technology transitions states only when AC power is connected or disconnected. It transitions by changing the CPU PLL multiplier, which can only be done in the Deep Sleep CPU state (clock going to the CPU is stopped), which is the C3 CPU power state.
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Most of the control for Intel SpeedStep technology is done in the ICH3-M. However, the GMCH-M must cooperate on certain functions.
5.5.7
5.5.7.1
Intel 830MP Chipset System "S" States
Powered-On-Suspend (POS) (S1)
The deepest level of power savings that can be achieved by only shutting down clocks occurs in the S1 State. The only clock remaining active in the system in the S1 State is the RTC clock. This clock is used to detect wake events and to run the hardware in the resume well in the ICH3-M used to reactivate the system. During the S1 State the CPU and GMCH-M power is on, however there is no activity, so the only power consumed is the leakage power. The Clock synthesizer is powered off, this shuts the clocks off in the Host, Memory, and I/O clock groups.
5.5.7.2
Suspend-To-RAM (STR) (S3)
The final level of power savings for the GMCH-M is achievable when the Host Clock, Memory Group, and I/O clock group clocks are shutdown and the GMCH-M is powered down. This occurs when the system transitions to the S3 state. During transition to the S3 state, first the STPCLK# is asserted and the Stop Grant cycle snooped by the GMCH-M and forwarded over Hub interface where it is received by the ICH3-M. At this point the GMCH-M is functioning in the C2 State. The GMCH-M places all of the SDRAM components into the self-refresh mode. After the GMCH-M has placed all of the SDRAM components in self refresh, it is safe to enter the STR State. The ICH3-M will then assert a signal, SLP_S1#, to the clock synthesizer to shutdown all of the clocks in the Host and Memory Clock Groups. The GMCH-M will assume that no AGP, AGP/PCI, or hub interface cycle (except special cycles) will occur while the GMCH-M is in the C3 State. The processor cannot snoop its caches to maintain coherency while in the C3 State. GMCH-M contains no isolation circuitry and MUST be powered down once STR is reached. If GMCHM is powered up and driving outputs to devices that are powered down, component damage will result.
5.5.7.3
S4 (SUSPEND TO DISK), S5 (Soft Off) State
The Intel 830MP chipset does not distinguish between Suspend to Ram (S3), Suspend to Disk (S4) and Soft Off (S5) states. From the 830MP perspective, entry and exit to S4 or S5 states, is the same as entry and exit to S3 state.
5.5.8
System Memory Dynamic CKE support
To reduce EMI and preserve battery life, clocks to unpopulated SO-DIMMs are turned off. The DRB registers are read to determine if the row is populated. Clocks are turned off in pairs because SM_CLK[1:0] go to one SO-DIMM, SM_CLK[3:2] go to another SO-DIMM.. The main memory SDRAMs are power managed during normal operation and in low power modes. Each row has a separate CKE (clock enable) pin that is used for power management. CKE is used to put the SDRAM rows into power down mode. Active power management is employed during normal operation. The memory setting is determined by the thermals of the system and the number of chips in a row. Following refresh, all SDRAMs are powered down except the one for which there is the first pending request, if any.
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5.5.9
GMCH-M Thermal Management
GMCH-M contains a bandwidth monitor on the SDRAM interfaces. If the bandwidth exceeds a programmed amount, the GMCH-M will automatically stall to avoid thermal problems.830MP. Intel will provide a CMTI software suite to profile system for optimal thermal management. Please contact local FAE for support.
5.5.9.1
System Bandwidth Monitoring and Throttling
The GMCH-M has the capability for bandwidth monitoring/throttle mechanism for the system memory interface. If the counter window exceeds the bandwidth threshold, then the SDRAM throttling mechanism will be invoked to limit the memory reads/writes to a lower bandwidth. The bandwidth monitoring mechanism consists of a counter to measure SDRAM bandwidth being used. Depending on what is being monitored, reads, and writes or both, a counter is incremented. If the number of read/writes during the monitoring period exceeds the value programmed, the throttling mechanism is invoked. If GMCH-M detects an idle cycle where no traffic is encountered during the throttling window, the counter decrements and no throttling takes place. Once the bandwidth reaches the determined bandwidth, the Intel 830MP chipset will start to throttle and continue throttling determined by the activity percentage. If the bandwidth never exceeds the set value, no throttling will take place. 830MP will exit the throttling mechanism and return to monitoring traffic where the process starts over again.
5.6
Clocking
GMCH-M has the following clocks: * 133-MHz Low voltage Differential HTCLK(#) for Processor Side Bus * 66.666-MHz 3.3V GBOUT Output Clock for external Hub/AGP/PCI buffer * 66.666-MHz 3.3V GBIN from external buffer for AGP/Hub interface
5.7
XOR Test Chains
Another feature of the 830MP chipset is the support for XOR Chain test modes. The XOR Chain test mode is used by product engineers during manufacturing and OEMs during board level connectivity tests. The main purpose of this test mode is to detect connectivity shorts between adjacent pins and to check proper bonding between I/O pads and I/O pins. There are 11 XOR test chains built into the 830MP chipset.
5.7.1.1
Test Mode Entry
Excluding the RAC chain, all that is required to prepare the GMCH-M for XOR chain testing is to pull DVOA_D[7] and G_PAR/ADD_DETECT high prior to deasserting PCIRST#. The following event sequence will put the GMCH-M into XOR testability mode: 1. Deassert PCIRST# high, deassert DVOA_D[11;8:6;4:3] low, assert G_PAR/ADD_DETECT high 2. Assert PCIRST# low; assert DVOA_D[7:6] high and maintain G_PAR/ADD_DETECT high 3. Deassert PCIRST# high
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4. 5.
XOR chain patterns can be applied to all GMCH-M interfaces (except for RAC) after PCIRST# is deasserted. DVOA_D[11;8:6;4:3] and G_PAR/ADD_DETECT can be "Don't care". See Figure 11 for more details.
Figure 11. XOR Chain Test Mode Entry Events Diagram
PCIRST# DVOA_D[3] DVOA_D[4] DVOA_D[6] DVOA_D[7] DVOA_D[8] DVOA_D[11] G_PAR
Don't care Don't care Don't care Don't care Don't care Don't care Don't care
The assertion of DVOA_D[6] high in Figure 11 is optional. The 830MP chipset supports dual ended termination for the CPU but only single ended termination is necessary when using the XOR test chains.
5.7.1.2
RAC Chain Initialization
On the RAC chain, special timing requirements need to be followed in order to use it. The event sequence (see Section 5.7.1.2) to enter test mode for the RAC chain is identical to that for all other chains and is shown in Figure 11 above. The application of test patterns to the inputs of the RAC chain must adhere to the timing requirements shown in Figure 12. Table 35 lists the minimum and maximum timings for the time parameters in Figure 12. This includes the maximum test enable (t1) and output propagation delays (t2), and minimum period for the application of a test pattern (t3).
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Figure 12. RAC Chain Timing Diagram
PCIRST# IOCTEn (internal signal) NC (ball F12) DQA DQB RQ CTM(CFM) CTMB(CFMB) X
t2
t1
t1
D0
t2
D1 D1
D0
t3
Table 35. RAC Chain Timing Descriptions
Symbol t1 t2 t3 Description IOCT test enable delay I/O to IOCT Output delay I/O connectivity sequence period Min 0 0 30 Max 100 25 ns ns ns Unit
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5.7.1.3
XOR Chain Test Pattern Consideration for Differential Pairs
Below are the differential signals in the XOR chains that must be treated as pairs. Pin1 and Pin2 as shown below must always be complementary to each other. For example, if a 1 is driven on ADSTB0, a 0 must be driven on ADSTB0# and vice versa. This will need to be considered when applying test patterns to these chains.
Table 36. XOR Chain Differential Pairs
Pin1 ADSTB0 ADSTB1 SBSTB DVOADATA(0) PSTRB Pin2 ADSTB0# ADSTB1# SBSTB# DVOADATA(1) PSTRB# XOR Chain AGP1 AGP1 AGP2 DVO Hublink
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5.7.1.4
XOR Chain Exclusion List
Please see below for a list of pins that are not included in the XOR chains (excluding all VCC/VSS): 1. 2. 3. 4. 5. 6. 7. 8. 9. GTL_REF0 GTL_RCOMP CPURST# GTL_REF1 HTCLK# HTCLK DREFCLK DVOA_RCOMP BLUE#
10. BLUE 11. GREEN 12. GREEN# 13. RED 14. RED# 15. GBIN 16. GBOUT 17. RESET# 18. AGP_RCOMP 19. AGPREF 20. HLREF 21. HL_RCOMP 22. SM_REF0 23. SM_REF1
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5.7.1.5
NC Balls
Beginning with the A3 stepping of the 830MP chipset, a ballout change was made to the chipset and a number of chipset features were defeatured. The resulting ballout change also resulted in four NC (No Connect) balls that are no longer used in any chipset features. However, these four NC balls are still used as input and/or output to some of the XOR test chains. The following table lists the balls and associated XOR chain.
Table 37. NC Ball and Associated XOR Chain
Ball 1 2 3 4 E11 E20 F20 F12 XOR Chain PSB2 SM1 SM1 RAC
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5.7.1.6
XOR Chain Connectivity/Ordering
The following tables contain the ordering for all of the 830MP chipset XOR chains and pin to ball mapping information:
Table 38. XOR Chain AGP1
Ball XOR OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A19 W25 Y29 V25 W26 W27 W29 V27 V28 V29 U26 U27 U29 U28 T25 T26 T27 T29 R24 R25 P29 N29 N27 N26 M29 M28 M27 M25 L29 L28 L27 L26 Pin SMA5 GAD29 GAD31 GAD27 GAD28 GAD30 GAD26 GAD22 GAD23 GAD25 GAD24 GAD21 GDSTB1 GDSTBB1 GCBE3 GAD20 GAD19 GAD18 GAD17 GAD16 GCBE1 GAD12 GAD15 GAD14 GAD8 GAD9 GAD11 GAD13 GDSTB0 GDSTBB0 GCBE0 GAD4
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32 33 34 35 36 37 38 39
K29 K27 K26 L24 J29 K25 J28 J27
GAD6 GAD7 GAD2 GAD10 GAD0 GAD3 GAD1 GAD5
Table 39. XOR Chain AGP2
Ball XOR OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A17 AD29 AB25 AC27 AC28 AC29 AA25 AB26 AB27 AB29 Y24 AA27 AA28 W24 AA24 Y26 AA29 Y27 Y28 R29 R27 R28 P28 P27 P26 N25 Pin SMA9 GGNTB GRBFB GREQB GST0 GST1 GSBA2 GPIPEB GST2 GWBFB GSBA3 GSBSTB GSBSTBB GSBA6 GSBA1 GSBA5 GSBA0 GSBA4 GSBA7 GFRAMEB GCBE2 GDEVSELB GPAR GTRDYB GIRDYB GSTOPB
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Table 40. XOR Chain DVO
Ball XOR OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C16 AD20 AE21 AJ22 AH22 AG22 AF22 AJ23 AE22 AH23 AG23 AF23 AD21 AJ24 AG24 AE23 AJ25 AE24 AH25 AG25 AJ26 Pin SMBA1 DVO CLKIN DVO INTR DVOD0 DVOD1 DVOD2 DVO HSYNC DVOD3 DVO FIELD DVOD4 DVOD5 DVO VSYNC DVO BLANK DVO CLK DVO CLKB DVOD6 DVOD8 DVOD7 DVOD9 DVOD10 DVOD11
Table 41. XOR Chain PSB1
Ball XOR OUT 1 2 3 4 5 6 7 8 9 E17 G6 D3 C1 H6 G5 F4 E3 G4 J6 Pin SMCS0 H_RS2B H_HITB H_ADSB H_RS0B H_DBSYB H_DRDYB H_A4 H_TRDYB H_LOCKB
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
D1 H4 G3 K6 E1 K5 F2 F1 L6 K4 H2 M6 L4 M4 N4 Y2 AA1 AA2 AA4 AB1 AB3 AC1 AC2 AC3 AC4 AA6 AD1 AD2 AD4 AE1 AE3 AF1 AF2 AC6 AE4 AB6 AF3 AG1
H_HITMB H_RS1B H_A5 H_REQ0B H_BNRB H_REQ2B H_A9 H_A8 H_REQ4B H_REQ3B H_A3 H_A7 H_BPRIB H_REQ1B H_A6 H_D32 H_D34 H_D38 H_D33 H_D36 H_D39 H_D45 H_D42 H_D49 H_D37 H_D35 H_D41 H_D40 H_D47 H_D59 H_D52 H_D63 H_D55 H_D44 H_D57 H_D43 H_D46 H_D58
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48 49 50 51 52 53 54 55 56
AG2 AE5 AD6 AF4 AG3 AH3 AG4 AH4 AJ3
H_D53 H_D51 H_D48 H_D54 H_D62 H_D50 H_D60 H_D61 H_D56
Table 42. XOR Chain PSB2
Ball XOR OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 E11 F3 J4 H3 G1 J3 H1 K3 L3 J2 J1 N5 M3 K1 L2 L1 M2 P6 N3 M1 P4 P3 N1 P2 P1 Pin NC H_A11 H_DEFERB H_A28 H_A13 H_A10 H_A15 H_A31 H_A23 H_A19 H_A25 H_A14 H_A29 H_A22 H_A20 H_A24 H_A18 H_A12 H_D6 H_A30 H_A16 H_D9 H_A26 H_D15 H_D1
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25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
R4 R3 R2 R1 T5 T4 T3 T1 U4 U6 U3 U2 U1 V4 V3 V2 V1 W4 W3 V6 W1 W5 Y3 Y4 W6 Y6 Y1 AA3 AB4 AD3 AB5
H_A21 H_D10 H_D17 H_D5 H_A27 H_A17 H_D14 H_D18 H_D0 H_D4 H_D20 H_D3 H_D11 H_D8 H_D16 H_D30 H_D24 H_D13 H_D19 H_D12 H_D23 H_D7 H_D31 H_D21 H_D2 H_D26 H_D25 H_D22 H_D28 H_D27 H_D29
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Table 43. XOR Chain GPIO
Ball XOR OUT 1 2 3 4 5 6 7 8 9 C15 AD28 AC24 AD27 AC25 AD26 AE29 AE27 AE26 AD25 Pin SMA11 HSYNC AGP BUSY DDC1 DATA I2C DATA DDC2 DATA VSYNC DDC1 CLK DDC2 CLK I2C CLK
Table 44. XOR Chain HUB
Ball XOR OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 A18 E28 G25 E29 F27 G26 F28 G29 G27 F29 H26 H27 H28 H29 Pin SMA4 HLD7 HLRQM HLD6 HLD5 HLD0 HLSTBB HLSTB HLRQI HLD4 HLSTOP HLD3 HLD1 HLD2
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Table 45. XOR Chain SM1
Ball XOR OUT 1 2 3 4 5 6 7 8 9 10 12 14 15 16 17 18 20 22 23 24 26 27 28 32 33 34 35 36 37 38 39 40 42 43 44 A20 C24 A24 G22 A23 D22 F21 D21 E20 F20 A22 B20 D19 F18 B19 C17 B17 D15 F13 A15 B14 D13 C13 A13 D12 A11 B11 B10 F11 A9 C9 D9 F10 B8 F9 B7 Pin SMA0 SMRCLK SMOCLK SMD42 SMD44 SMD43 SMD45 SMD46 NC NC SMD47 SMA1 SMCAS SMDQM0 SMA2 SMA6 SMA8 SMCS3 SMDQM7 SMCLK0 SMCLK2 SMDQM2 SMCKE2 SMCKE0 SMDQM3 SMD49 SMD50 SMD52 SMD48 SMCKE3 SMCKE1 SMD54 SMD51 SMD53 SMD56 SMD55
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45 46 47 48 49 50 51 53 54
D7 A6 C6 E6 B5 A4 A3 B2 D4
SMD59 SMD57 SMD58 SMD61 SMD60 SMD62 SMCLK3 SMCLK1 SMD63
Table 46. XOR Chain SM2
Ball XOR OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C19 D29 C29 C28 B28 E27 D27 E26 C27 A27 C26 B26 E24 A26 D25 C25 B25 E23 D24 A25 F23 C23 B23 F22 C22 Pin SMA3 SMD0 SMD1 SMD33 SMD34 SMD32 SMD2 SMD35 SMD3 SMD4 SMD36 SMD5 SMD6 SMD38 SMD37 SMD7 SMD9 SMD8 SMD39 SMD41 SMD40 SMD10 SMD12 SMD11 SMD13
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25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
E21 B22 A21 C20 E18 D18 F17 C18 D16 B16 A16 C14 F14 C12 C11 A10 C10 D10 F8 E9 C8 A7 C7 E8 D6 A5 C5 B4 C4
SMD14 SMD15 SMWE SMRAS SMDQM4 SMDQM1 SMDQM5 SMA7 SMCS2 SMBA0 SMA10 SMA12 SMDQM6 SMD16 SMD18 SMD19 SMD20 SMD17 SMD27 SMD23 SMD21 SMD22 SMD24 SMD25 SMD29 SMD26 SMD28 SMD30 SMD31
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Table 47. XOR Chain CMOS
Ball XOR OUT 1 2 3 4 5 F16 AG6 AJ6 AF7 AH7 AJ7 Pin SMCS1 GCLK RCLK SCK CMD SIO
Table 48. XOR Chain RAC
Ball XOR OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 F12 AJ20 AG20 AJ19 AG19 AJ18 AG18 AJ17 AG17 AH15 AJ16 AJ15 AH16 AJ14 AG14 AJ13 AG13 AH13 AG12 AJ12 AG11 AJ11 AH10 AJ10 AG10 AJ9 Pin NC DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CTM CFM CTM_B CFM_B RQ7 RQ6 RQ5 RQ4 RQ3 RQ2 RQ1 RQ0 DQB0 DQB1 DQB2 DQB3 DQB4
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26 27 28
AG9 AJ8 AG8
DQB5 DQB6 DQB7
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6
Performance
The system performance for the Intel 830MP chipset GMCH-M described below is a breakdown of the data streams that complement both the mobile Intel Pentium III Processor-M. This section describes the overall performance of the GMCH-M. Following categories of performance are examined: * CPU/830MP GMCH-M: Intel 830MP chipset supports mobile Intel Pentium III Processor-M * System Memory: Intel 830MP chipset GMCH-M supports PC133 main memory
Table 49. System Bandwidths
Interface Clock Speed (MHz) CPU Bus SDRAM AGP 2.0 DVO PCI 2.2 NOTE: 133 133 66 165 33 Samples Per Clock 1 1 4 2 1 Data Rate (Mega-samples/s) 133 133 266 330 33 Data Width (Bytes) 8 8 4 1.5 4 Bandwidth (MB/s) 1066 1064 1066 495 133
*Theoretical Bandwidths only.
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7.1
Mechanical Specification
Intel 830MP Chipset GMCH-M Ballout Diagram
Figure 13 and Figure 14 show the ballout of the GMCH-M.
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Figure 13. Intel 830MP Chipset Ballout (Left Side)
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ 1
H_ADS#
2
3
SM_CLK3
4
SMD62 SMD30 SMD31
5
SMD26 SMD60 SMD28
6
SMD57 VSS SMD58
7
SMD22 SMD55 SMD24
8
VCC_SM SMD53 SMD21
9
SM_CKE3 VSS SM_CKE1
10
SMD19 SMD52 SMD20
11
SMD49 SMD50 SMD18
12
VCC_SM VSS SMD16
13
SM_CKE0 VSS SM_CKE2
14
VSS SM_CLK2 SMA12
SM_CLK1 GTL_ RCOMP H_HITM# H_BNR# H_A8# H_A13# VSS VTT H_A9# VSS
VSS VSS
H_HIT# H_A4# H_A11# H_A5#
SMD63 VSS H_DRDY# H_TRDY#
VCC_SM SM_VREF1 VTT H_DBSY#
SMD29 SMD61 SM_RCOMP H_RS2#
SMD59 VSS VCCQ_SM VCCA_ CPLL
VCC_SM SMD25 SMD27 VSSA_CPLL
SMD54 SMD23 SMD56 VSS
SMD17 VSS SMD51 VCC_SM
VCC_SM NC SMD48 VCC_SM
SM_DQM3 VCC_SM NC
SM_DQM2 VSS SM_DQM7
VCC_SM VSS SM_DQM6
H_A15# H_A25# H_A22# H_A24# H_A30# H_A26# H_D1# H_D5# H_D18# H_D11# H_D24# H_D23# H_D25# H_D34# H_D36# H_D45# H_D41# H_D59#
H_A3# H_A19# VSS H_A20# H_A18# VSS H_D15# H_D17# VSS H_D3# H_D30# VSS H_D32# H_D38# VSS H_D42# H_D40# VSS
H_A28# H_A10# H_A31# H_A23# H_A29# H_D6# H_D9# H_D10# H_D14# H_D20# H_D16# H_D19# H_D31# H_D22# H_D39# H_D49# H_D27# H_D52#
H_RS1# H_DEFER# H_REQ3# H_BPRI# H_REQ1# H_A6# H_A16# H_A21# H_A17# H_D0# H_D8# H_D13# H_D21# H_D33# H_D28# H_D37# H_D47# H_D57#
VSS VTT H_REQ2# VSS VTT H_A14# VSS VTT H_A27# VSS VTT H_D7# VSS VTT H_D29# VSS VTT H_D51#
H_RS0# H_LOCK# H_REQ0# H_REQ4# H_A7# VCC H_A12# CPU_RST# VCC H_D4# H_D12# H_D2# H_D26# H_D35# H_D43# H_D44# H_D48# VCCA_ HPLL
VCC GTL_REFA VCC VCC VSS VSS VCC VCC VCC VSS VSS VCC VCC GTL_REFB VCC VSS VSSA_HPLL VCC_CMOS VCC_CMOS VSS VSS VCC_CMOS VSS VSS VCC_LM VSS VSS VCC_LM VCC_LM VSS VCC_LM VSS VCC_LM VSS RAMREF RAMREF VSS VSS VSS VSS VSS VSS VSS VCC VSS VSS VSS VSS VSS VDD_LM
H_D63# H_D58#
H_D55# H_D53# VSS
H_D46# H_D62# H_D50# H_D56#
H_D54# H_D60# H_D61# HTCLK
VSS VTT HTCLK# VSS
VCC_CMOS GCLK VSS GM_RCLK
SCK VSS CMD SIO
VSS DQB7 VSS DQB6
VSS DQB5 VSS DQB4
VSS DQB3 DQB1 DQB2
VSS RQ0 VSS DQB0
VSS RQ2 VSS RQ1
VSS RQ4 RQ3 RQ5
VSS RQ6 VSS RQ7
2
3
4
5
6
7
8
9
10
11
12
13
14
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Figure 14. Intel 830MP Chipset Ballout (Right Side)
15
SM_ CLK0 VSS SMA11 SM_CS3# VCCQ_ SM VCCQ_ SM VCCQ_SM VCCQ_SM VSS SMD42 VCC_SM VSSA_ DPLL1 VCC HRCOMP VCC HLREF VCC_HUB AGP_ RCOMP VCC_AGP VCC VSS VSS VSS VSS VSS VDD_LM VCC VSS VSS VSS VSS VSS VDD_LM VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VSS VDDQ_AGP VCC VCC_AGP VSS DREFCLK VCCA_ DPLL0 VDD_LM VDD_LM VCC_LM VCC_LM VCC_LM DVO_ CLKIN VDD_LM VDD_LM VSS VCC_LM VSS VSSA_DPLL 0 VSS VSS VSS VSS VSS VSS VCC_DVO DVO_HSYNC DVO_VSYNC VCC_DVO DVO_ BLANK DVO_INTR DVO_FIELD DVO_D6 DVO_D7 VCC_ GPIO VSS VCCA_ DAC VSS VSS DQA0 DQA2 DQA4 DQA6 VSS DVO_D2 DVO_D5 DVO_CLK# DVO_D10 GBIN VCCA_ DAC CTM CTM# CFM# CFM VSS DQA1 VSS DQA3 VSS DQA5 VSS DQA7 VSS VSS DVO_D1 DVO_D0 DVO_D4 DVO_D3 VSS DVO_CLK DVO_D9 DVO_D8 VSSA_DAC DVO_D11 BLUE# REFSET BLUE GREEN# GREEN VSS RED# RED DDC2_CK DDC1_CK VSS VSYNC VSS VCC_GPIO GBOUT VCC_DVO DVO_RCOMP VSS G_AD10 VCC VCCQ_AGP VCC G_AD17 VCC VCC_AGP VCC SBA6 SBA3 SBA1 RESET# AGPBUSY# VSS G_AD13 G_STOP# VSS G_AD16 G_CBE3# VSS G_AD27 G_AD29 VSS SBA2 RBF# I2C_ DATA I2C_CLK DDC2_DA DDC1_DA HSYNC G_GNT# G_AD4 VCC_ AGP G_AD14 G_IRDY# VCC_ AGP G_AD20 G_AD24 VCC_ AGP G_AD28 SBA5 VCC_ AGP PIPE# VSS G_CBE0# G_AD11 G_AD15 G_TRDY# G_CBE2# G_AD19 G_AD21 G_AD22 G_AD30 SBA4 SB_STB ST2 REQ# AD_STB0# G_AD9 VSS G_PAR AD_STB0 G_AD8 G_AD12 G_CBE1# VSS AGPREF G_AD3 HL10 VCC_ AGP G_AD2 HL3 G_AD5 G_AD7 HL1 G_AD1 VSS HL2 G_AD0 G_AD6 SM_CS1# SMDQM5 SMDQM0 VSS NC SMD45 SMD11 SMD40 SM_VREF0 VCCA_ PLL1 HL8 HL0 HL9 VSS HLSTRB VCC_ HUB HL5 HLSTRB# HL4 SMBA0 SMBA1 SM_CS2# VSS SMA8 SMA6 VCC_SM SM_CS0# VSS SMA7 SMDQM1 SMDQM4 SMA2 SMA3 SMCAS VSS SMA1 SMRAS VCC_SM NC VSS VSS SMD46 SMD14 SMD15 SMD13 SMD43 VSS SMD12 SMD10 VCC_SM SMD8 VSS SM_RCLK SMD39 SMD6 SMD9 SMD7 SMD37 VSS SMD5 SMD36 VCC_SM SMD35 VSS SMD3 SMD2 SMD32 SMD34 SMD33 VSS HL7 SMD1 SMD0 HL6
16
SMA10
17
SMA9
18
SMA4
19
SMA5
20
SMA0
21
SMWE
22
SMD47
23
SMD44
24
SM_OCLK
25
SMD41
26
SMD38
27
SMD4
28
29 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ
G_DEVSEL# G_FRAME# VSS AD_STB1# G_AD23 VSS SBA7 SB_STB# VSS ST0 G_AD18 AD_STB1 G_AD25 G_AD26 G_AD31 SBA0 WBF# ST1
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7.2
Intel 830MP Chipset GMCH-M Signal List
Table 50 provides an alphabetical signal listing of the GMCH-M ballouts.
Table 50. Intel 830MP Chipset Ballout Signal Name List
Ball # L29 L28 U29 U28 C1 AC24 K24 J25 AH28 AH27 E1 L4 AJ16 AH16 AH7 R6 AH15 AJ15 G5 AE27 AD27 AE26 AD26 J4 AG17 AJ17 AG18 AJ18 AG19 AJ19
Signal Name AD_STB0 AD_STB0# AD_STB1 AD_STB1# ADS# AGPBUSY# AGP_RCOMP AGPREF BLUE BLUE# BNR# BPRI# CFM CFM# CMD CPURST# CTM CTM# DBSY# DDC1_CLK DDC1_DATA DDC2_CLK DDC2_DATA DEFER# DQ_A0 DQ_A1 DQ_A2 DQ_A3 DQ_A4 DQ_A5
AG20 AJ20 AJ11 AH10 AJ10 AG10 AJ9 AG9 AJ8 AG8 F4 AC19 AD20 AD21 AG24 AJ24 AJ22 AH22 AG25 AJ26 AG22 AJ23 AH23 AG23 AE23 AE24 AJ25 AH25 AE22 AF22 AE21
DQ_A6 DQ_A7 DQ_B0 DQ_B1 DQ_B2 DQ_B3 DQ_B4 DQ_B5 DQ_B6 DQ_B7 DRDY# DREFCLK DV0A_CLKINT DVOA_BLANK# DVOA_CLK# DVOA_CLK DVOA_D0 DVOA_D1 DVOA_D10 DVOA_D11 DVOA_D2 DVOA_D3 DVOA_D4 DVOA_D5 DVOA_D6 DVOA_D7 DVOA_D8 DVOA_D9 DVOA_FLD/STL DVOA_HSYNC DVOA_INTR#
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AC22 AF23 J29 J28 L24 M27 N29 M25 N26 N27 R25 R24 T29 T27 K26 T26 U27 V27 V28 U26 V29 W29 V25 W26 W25 K25 W27 Y29 L26 J27 K29 K27 M29 M28 L27 P29 R27 T25
DVOA_RCOMP DVOA_VSYNC G_AD0 G_AD1 G_AD10 G_AD11 G_AD12 G_AD13 G_AD14 G_AD15 G_AD16 G_AD17 G_AD18 G_AD19 G_AD2 G_AD20 G_AD21 G_AD22 G_AD23 G_AD24 G_AD25 G_AD26 G_AD27 G_AD28 G_AD29 G_AD3 G_AD30 G_AD31 G_AD4 G_AD5 G_AD6 G_AD7 G_AD8 G_AD9 G_C/BE0# G_C/BE1# G_C/BE2# G_C/BE3#
R28 R29 AD29 P26 P28 AC27 N25 P27 AG26 AD24 AG6 AJ6 AG29 AG28 C2 J7 AA7 J3 F3 P6 G1 N5 H1 P4 T4 M2 J2 L2 R4 K1 L3 L1 J1 N1 T5 H3 M3 H2
G_DEVSEL# G_FRAME# G_GNT# G_IRDY# G_PAR G_REQ# G_STOP# G_TRDY# GBIN GBOUT GM_GCLK GM_RCLK GREEN GREEN# GTL_RCOMP GTL_REFA GTL_REFB HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA3#
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151
Intel 830MP Chipset
(R)
R
M1 K3 E3 G3 N4 M6 F1 F2 U4 P1 R3 U1 V6 W4 T3 P2 V3 R2 T1 W3 W6 U3 Y4 AA3 W1 V1 Y1 Y6 AD3 AB4 AB5 U2 V2 Y3 Y2 AA4 AA1 AA6
HA30# HA31# HA4# HA5# HA6# HA7# HA8# HA9# HD0# HD1# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD2# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD3# HD30# HD31# HD32# HD33# HD34# HD35#
AB1 AC4 AA2 AB3 U6 AD2 AD1 AC2 AB6 AC6 AC1 AF3 AD4 AD6 AC3 R1 AH3 AE5 AE3 AG2 AF4 AF2 AJ3 AE4 AG1 AE1 N3 AG4 AH4 AG3 AF1 W5 V4 P3 D3 D1 J23 H24
HD36# HD37# HD38# HD39# HD4# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD5# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD6# HD60# HD61# HD62# HD63# HD7# HD8# HD9# HIT# HITM# HL_RCOMP HLREF
152
Datasheet
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R
Intel 830MP Chipset
(R)
G26 H28 H26 H29 H27 F29 F27 E29 E28 G25 G27 J6 G29 F28 K6 M4 K5 K4 L6 AD28 AJ4 AH5 G4 AD25 AC25 E11 E20 F12 F20 AB26 AD14 AE14 AB25 AF29 AF28 AJ27 AB24 AG11
HL0 HL1 HL10 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HLOCK# HLSTRB HLSTRB# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HSYNC HTCLK HTCLK# HTRDY# I2C_CLK I2C_DATA NC NC NC NC PIPE# RAM_REFA RAM_REFB RBF# RED RED# REFSET RESET# RQ0
AJ12 AG12 AH13 AG13 AJ13 AG14 AJ14 H6 H4 G6 AA27 AA28 AA29 AA24 AA25 Y24 Y27 Y26 W24 Y28 AF7 AJ7 B16 C16 D19 A13 C9 C13 A9 A15 B2 B14 A3 E17 F16 D16 D15 F18
RQ1 RQ2 RQ3 RQ4 RQ5 RQ6 RQ7 RS0# RS1# RS2# SB_STB SB_STB# SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 SCK SIO SM_BA0 SM_BA1 SM_CAS# SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 SM_CLK0 SM_CLK1 SM_CLK2 SM_CLK3 SM_CS0# SM_CS1# SM_CS2# SM_CS3# SM_DQM0
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153
Intel 830MP Chipset
(R)
R
D18 D13 D12 E18 F17 F14 F13 A20 B20 A16 C15 C14 B19 C19 A18 A19 C17 C18 B17 A17 D29 C29 C23 F22 B23 C22 E21 B22 C12 D10 C11 A10 D27 C10 C8 A7 E9 C7
SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7 SM_MA0 SM_MA1 SM_MA10 SM_MA11 SM_MA12 SM_MA2 SM_MA3 SM_MA4 SM_MA5 SM_MA6 SM_MA7 SM_MA8 SM_MA9 SM_MD0 SM_MD1 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD2 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24
E8 A5 F8 C5 D6 C27 B4 C4 E27 C28 B28 E26 C26 D25 A26 D24 A27 F23 A25 G22 D22 A23 F21 D21 A22 F11 A11 B26 B11 F10 B10 B8 D9 B7 F9 A6 C6 D7
SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29 SM_MD3 SM_MD30 SM_MD31 SM_MD32 SM_MD33 SM_MD34 SM_MD35 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD4 SM_MD40 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD5 SM_MD50 SM_MD51 SM_MD52 SM_MD53 SM_MD54 SM_MD55 SM_MD56 SM_MD57 SM_MD58 SM_MD59
154
Datasheet
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R
Intel 830MP Chipset
(R)
E24 B5 E6 A4 D4 C25 E23 B25 A24 C20 C24 F6 E5 F24 A21 AC28 AC29 AB27 N6 T6 H7 K7 L7 W7 Y7 AB7 P12 R12 T12 M14 M15 M16 P18 R18 T18 H23 K23 Y23
SM_MD6 SM_MD60 SM_MD61 SM_MD62 SM_MD63 SM_MD7 SM_MD8 SM_MD9 SM_OCLK SM_RAS# SM_RCLK SM_RCOMP SM_REFA SM_REFB SM_WE# ST0 ST1 ST2 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
M24 P24 T24 V24 L23 U24 J26 M26 R26 V26 AA23 AA26 AC8 AC9 AE7 AF6 AC21 AF21 AF24 AD23 AE25 J24 F26 AC10 AC11 AD11 AD12 AD13 AD17 AD18 AD19 AE18 D5 D8 D11 G11 D14 D17
VCC VCC VCC VCC VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_CMOS VCC_CMOS VCC_CMOS VCC_CMOS VCC_DVO VCC_DVO VCC_DVO VCC_GPIO VCC_GPIO VCC_HUB VCC_HUB VCC_LM VCC_LM VCC_LM VCC_LM VCC_LM VCC_LM VCC_LM VCC_LM VCC_LM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
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155
Intel 830MP Chipset
(R)
R
D20 D23 G23 D26 G10 E12 A8 A12 G7 AF26 AG27 AC20 F25 AE6 W23 N24 E15 F7 F15 G19 G20 V14 V15 V16 AD15 AD16 AE15 AE16 A14 B13 C3 C21 E14 F19 D2 G2 K2 N2
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCCA_CPLL VCCA_DAC VCCA_DAC VCCA_DPLL0 VCCA_DPLL1 VCCA_HPLL VCCQ_AGP VCCQ_AGP VCCQ_SM VCCQ_SM VCCQ_SM VCCQ_SM VCCQ_SM VDD_LM VDD_LM VDD_LM VDD_LM VDD_LM VDD_LM VDD_LM VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
T2 W2 AB2 AE2 AH2 B3 E4 H5 L5 P5 U5 Y5 AC5 AF5 AJ5 B6 AH6 E7 AC7 AG7 AD8 AE8 AF8 AH8 B9 G9 AD9 AE9 AF9 AH9 E10 AD10 AE10 AF10 AE11 AF11 AH11 B12
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
156
Datasheet
298338-001
R
Intel 830MP Chipset
(R)
M12 N12 U12 V12 AE12 AF12 AH12 E13 M13 N13 P13 R13 T13 U13 V13 AE13 AF13 N14 P14 R14 T14 U14 AF14 AH14 B15 N15 P15 R15 T15 U15 AF15 AG15 E16 N16 P16 R16 T16 U16
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AF16 AG16 M17 N17 P17 R17 T17 U17 V17 AE17 AF17 AH17 B18 M18 N18 U18 V18 AF18 AH18 E19 AE19 AF19 AH19 AF20 AH20 B21 G21 AG21 AH21 AJ21 E22 AD22 AB23 AC23 B24 AH24 E25 H25
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Datasheet
157
Intel 830MP Chipset
(R)
R
L25 P25 U25 Y25 AF25 AC26 B27 AF27 D28 G28 K28 N28 T28 W28 AB28 AE28 G8 AH26 AE20 G24 AD7 AE29 E2 F5 J5 M5 R5 V5 AA5 AD5 AG5 AB29
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA_CPLL VSSA_DAC VSSA_DPLL0 VSSA_DPLL1 VSSA_HPLL VSYNC VTT VTT VTT VTT VTT VTT VTT VTT VTT WBF#
158
Datasheet
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R
Intel 830MP Chipset
(R)
7.3
Intel 830MP Chipset Package Dimensions
Figure 15 outlines the mechanical dimensions for the Intel 830MP chipset GMCH-M. The package is a 625-ball grid array (BGA) package.
Figure 15. Intel 830MP Chipset GMCH-M Package Dimensions
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